SVA: The Power of Assertions in SystemVerilog
This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis. The book provide...
Κύριοι συγγραφείς: | Cerny, Eduard (Συγγραφέας), Dudani, Surrendra (Συγγραφέας), Havlicek, John (Συγγραφέας), Korchemny, Dmitry (Συγγραφέας) |
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Συγγραφή απο Οργανισμό/Αρχή: | SpringerLink (Online service) |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Cham :
Springer International Publishing : Imprint: Springer,
2015.
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Έκδοση: | 2nd ed. 2015. |
Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Παρόμοια τεκμήρια
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The Power of Assertions in SystemVerilog
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SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications /
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ανά: Chen, Weiwei
Έκδοση: (2015)