SVA: The Power of Assertions in SystemVerilog

• Κύριοι συγγραφείς: Cerny, Eduard (Συγγραφέας), Dudani, Surrendra (Συγγραφέας), Havlicek, John (Συγγραφέας), Korchemny, Dmitry (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2015.
• Έκδοση: 2nd ed. 2015.
• Θέματα: Engineering.; Microprocessors.; Electronic circuits.; Circuits and Systems.; Processor Architectures.; Electronic Circuits and Devices.

This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA).  It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis.  The book provide...

Πίνακας περιεχομένων:

• Part I. Opening
• Introduction
• System Verilog Language and Overview
• System Verilog Simulation Semantics
• Part II. Basic Assertions
• Assertion Statements
• Basic Properties
• Basic Sequences
• Assertion System Functions and Tasks
• Part III. Metalanguage Constructs
• Let, Sequence and Property Declarations; Inference.- Checkers
• Part IV. Advanced Assertions
• Advanced Properties
• Advanced Sequences.- Clocks
• Resets
• Procedural Concurrent Assertions.- An Apology for Local Variables
• Mechanics of Local Variables
• Recursive Properties
• Coverage
• Debugging Assertions and Efficiency Considerations
• Part V. Formal Verification
• Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers
• Checkers in Formal Verification.- Checker Libraries
• Appendix
• References.- Index.