Advanced Hardware Design for Error Correcting Codes

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Άλλοι συγγραφείς: Chavet, Cyrille (Επιμελητής έκδοσης), Coussy, Philippe (Επιμελητής έκδοσης)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2015.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
LEADER 03402nam a22004695i 4500
001 978-3-319-10569-7
003 DE-He213
005 20151204162208.0
007 cr nn 008mamaa
008 141030s2015 gw | s |||| 0|eng d
020 |a 9783319105697  |9 978-3-319-10569-7 
024 7 |a 10.1007/978-3-319-10569-7  |2 doi 
040 |d GrThAP 
050 4 |a TK7888.4 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
082 0 4 |a 621.3815  |2 23 
245 1 0 |a Advanced Hardware Design for Error Correcting Codes  |h [electronic resource] /  |c edited by Cyrille Chavet, Philippe Coussy. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2015. 
300 |a IX, 192 p. 81 illus., 25 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.                                                                                                                                       . 
520 |a This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou. 
650 0 |a Engineering. 
650 0 |a Computers. 
650 0 |a Electrical engineering. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Communications Engineering, Networks. 
650 2 4 |a Information Systems and Communication Service. 
700 1 |a Chavet, Cyrille.  |e editor. 
700 1 |a Coussy, Philippe.  |e editor. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9783319105680 
856 4 0 |u http://dx.doi.org/10.1007/978-3-319-10569-7  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)