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03447nam a22004935i 4500 |
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978-3-319-22035-2 |
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150827s2016 gw | s |||| 0|eng d |
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|a 9783319220352
|9 978-3-319-22035-2
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|a 10.1007/978-3-319-22035-2
|2 doi
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|d GrThAP
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|a TK7888.4
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|a TJFC
|2 bicssc
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|a TEC008010
|2 bisacsh
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|a 621.3815
|2 23
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|a Mohamed, Khaled Salah.
|e author.
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|a IP Cores Design from Specifications to Production
|h [electronic resource] :
|b Modeling, Verification, Optimization, and Protection /
|c by Khaled Salah Mohamed.
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264 |
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1 |
|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2016.
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300 |
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|a IX, 154 p. 153 illus., 115 illus. in color.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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|a text file
|b PDF
|2 rda
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|a Analog Circuits and Signal Processing,
|x 1872-082X
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|a 1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.
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|a This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies. · Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; · Introduce a deep introduction for Verilog for both implementation and verification point of view. · Demonstrates how to use IP in applications such as memory controllers and SoC buses. · Describes a new verification methodology called bug localization; · Presents a novel scan-chain methodology for RTL debugging; · Enables readers to employ UVM methodology in straightforward, practical terms.
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650 |
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|a Engineering.
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650 |
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|a Microprocessors.
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650 |
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0 |
|a Electronics.
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650 |
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|a Microelectronics.
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650 |
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|a Electronic circuits.
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650 |
1 |
4 |
|a Engineering.
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650 |
2 |
4 |
|a Circuits and Systems.
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650 |
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4 |
|a Processor Architectures.
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650 |
2 |
4 |
|a Electronics and Microelectronics, Instrumentation.
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710 |
2 |
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|a SpringerLink (Online service)
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773 |
0 |
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|t Springer eBooks
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776 |
0 |
8 |
|i Printed edition:
|z 9783319220345
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830 |
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|a Analog Circuits and Signal Processing,
|x 1872-082X
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856 |
4 |
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|u http://dx.doi.org/10.1007/978-3-319-22035-2
|z Full Text via HEAL-Link
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912 |
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|a ZDB-2-ENG
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950 |
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|a Engineering (Springer-11647)
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