Microfluidic Very Large Scale Integration (VLSI) Modeling, Simulation, Testing, Compilation and Physical Synthesis /

• Κύριοι συγγραφείς: Pop, Paul (Συγγραφέας), Minhass, Wajid Hassan (Συγγραφέας), Madsen, Jan (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2016.
• Έκδοση: 1st ed. 2016.
• Θέματα: Engineering.; Electronic circuits.; Biomedical engineering.; Circuits and Systems.; Biomedical Engineering.; Electronic Circuits and Devices.

 This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques presented, including solutions to the basic compilation and synthesis problems; · Discusses several new research problems in detail, using numerous examples. 

 Introduction -- Part 1. Preliminaries -- Design Methodology for Flow-based Microfluidic Biochips -- Biochip Architecture Model -- Biochemical Application Modeling -- Part 2. Compilation -- Compiling High-Level Languages -- Application Mapping and Simulation -- Control Synthesis and Pin-Count Minimization -- Part 3. Physical Design -- Allocation and Schematic Design -- Placement and Routing -- On-Chip Control Synthesis -- Testing and Fault-Tolerant Design.