Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offs /

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory cont...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Goossens, Sven (Συγγραφέας), Chandrasekar, Karthik (Συγγραφέας), Akesson, Benny (Συγγραφέας), Goossens, Kees (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2016.
Σειρά:Embedded Systems,
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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100 1 |a Goossens, Sven.  |e author. 
245 1 0 |a Memory Controllers for Mixed-Time-Criticality Systems  |h [electronic resource] :  |b Architectures, Methodologies and Trade-offs /  |c by Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2016. 
300 |a XXVII, 202 p. 78 illus. in color.  |b online resource. 
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505 0 |a Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols. 
520 |a This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. 
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650 2 4 |a Processor Architectures. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
700 1 |a Chandrasekar, Karthik.  |e author. 
700 1 |a Akesson, Benny.  |e author. 
700 1 |a Goossens, Kees.  |e author. 
710 2 |a SpringerLink (Online service) 
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830 0 |a Embedded Systems,  |x 2193-0155 
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