Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

• Main Authors: Meinerzhagen, Pascal (Author, http://id.loc.gov/vocabulary/relators/aut), Teman, Adam (http://id.loc.gov/vocabulary/relators/aut), Giterman, Robert (http://id.loc.gov/vocabulary/relators/aut), Edri, Noa (http://id.loc.gov/vocabulary/relators/aut), Burg, Andreas (http://id.loc.gov/vocabulary/relators/aut), Fish, Alexander (http://id.loc.gov/vocabulary/relators/aut)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Cham : Springer International Publishing : Imprint: Springer, 2018.
• Edition: 1st ed. 2018.
• Subjects: Electronic circuits.; Computer memory systems.; Electronics.; Microelectronics.; Circuits and Systems.; Memory Structures.; Electronics and Microelectronics, Instrumentation.

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed...

Table of Contents:

• Motivation
• Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs)
• GC-eDRAMs Operated at Scaled Supply Voltages
• Near-VT GC-eDRAM Implementations with Extended Retention Times
• Aggressive Technology and Voltage Scaling (to Sub-VT Domain)
• Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
• 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes
• Multilevel GC-eDRAM (MLGC-eDRAM)
• Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction
• Conclusions.