Symbolic Parallelization of Nested Loop Programs

This book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, fo...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Tanase, Alexandru-Petru (Συγγραφέας, http://id.loc.gov/vocabulary/relators/aut), Hannig, Frank (http://id.loc.gov/vocabulary/relators/aut), Teich, Jürgen (http://id.loc.gov/vocabulary/relators/aut)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2018.
Έκδοση:1st ed. 2018.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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100 1 |a Tanase, Alexandru-Petru.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Symbolic Parallelization of Nested Loop Programs  |h [electronic resource] /  |c by Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich. 
250 |a 1st ed. 2018. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2018. 
300 |a XII, 176 p. 33 illus. in color.  |b online resource. 
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505 0 |a Introduction -- Fundamentals and Compiler Framework -- Symbolic Parallelization -- Symbolic Multi‐level Parallelization -- On‐demand Fault‐tolerant Loop Processing -- Conclusions. 
520 |a This book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, for cases where the number of available cores becomes known only at runtime. The compile/runtime symbolic parallelization approach the authors describe reduces significantly the runtime overhead, compared to dynamic or just‐in-time compilation. The new, on‐demand fault‐tolerant loop processing approach described in this book protects loop nests for parallel execution against soft errors. . 
650 0 |a Electronic circuits. 
650 0 |a Microprocessors. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 1 4 |a Circuits and Systems.  |0 http://scigraph.springernature.com/things/product-market-codes/T24068 
650 2 4 |a Processor Architectures.  |0 http://scigraph.springernature.com/things/product-market-codes/I13014 
650 2 4 |a Electronics and Microelectronics, Instrumentation.  |0 http://scigraph.springernature.com/things/product-market-codes/T24027 
700 1 |a Hannig, Frank.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
700 1 |a Teich, Jürgen.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
710 2 |a SpringerLink (Online service) 
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776 0 8 |i Printed edition:  |z 9783319739083 
776 0 8 |i Printed edition:  |z 9783319739106 
776 0 8 |i Printed edition:  |z 9783030088842 
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950 |a Engineering (Springer-11647)