Computer Aided Verification 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004. Proceedings /

Λεπτομέρειες βιβλιογραφικής εγγραφής
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Άλλοι συγγραφείς: Alur, Rajeev (Επιμελητής έκδοσης), Peled, Doron A. (Επιμελητής έκδοσης)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg, 2004.
Σειρά:Lecture Notes in Computer Science, 3114
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
LEADER 04861nam a22006015i 4500
001 978-3-540-27813-9
003 DE-He213
005 20151204185150.0
007 cr nn 008mamaa
008 121227s2004 gw | s |||| 0|eng d
020 |a 9783540278139  |9 978-3-540-27813-9 
024 7 |a 10.1007/b98490  |2 doi 
040 |d GrThAP 
050 4 |a QA75.5-76.95 
072 7 |a UY  |2 bicssc 
072 7 |a UYA  |2 bicssc 
072 7 |a COM014000  |2 bisacsh 
072 7 |a COM031000  |2 bisacsh 
082 0 4 |a 004.0151  |2 23 
245 1 0 |a Computer Aided Verification  |h [electronic resource] :  |b 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004. Proceedings /  |c edited by Rajeev Alur, Doron A. Peled. 
264 1 |a Berlin, Heidelberg :  |b Springer Berlin Heidelberg,  |c 2004. 
300 |a XII, 536 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
490 1 |a Lecture Notes in Computer Science,  |x 0302-9743 ;  |v 3114 
505 0 |a Rob Tristan Gerth: 1956–2003 -- Static Program Analysis via 3-Valued Logic -- Deductive Verification of Pipelined Machines Using First-Order Quantification -- A Formal Reduction for Lock-Free Parallel Algorithms -- An Efficiently Checkable, Proof-Based Formulation of Vacuity in Model Checking -- Termination of Linear Programs -- Symbolic Model Checking of Non-regular Properties -- Proving More Properties with Bounded Model Checking -- Parallel LTL-X Model Checking of High-Level Petri Nets Based on Unfoldings -- Using Interface Refinement to Integrate Formal Verification into the Design Cycle -- Indexed Predicate Discovery for Unbounded System Verification -- Range Allocation for Separation Logic -- An Experimental Evaluation of Ground Decision Procedures -- DPLL(T): Fast Decision Procedures -- Verifying ?-Regular Properties of Markov Chains -- Statistical Model Checking of Black-Box Probabilistic Systems -- Compositional Specification and Model Checking in GSTE -- GSTE Is Partitioned Model Checking -- Stuck-Free Conformance -- Symbolic Simulation, Model Checking and Abstraction with Partially Ordered Boolean Functional Vectors -- Functional Dependency for Verification Reduction -- Verification via Structure Simulation -- Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures -- Abstraction-Based Satisfiability Solving of Presburger Arithmetic -- Widening Arithmetic Automata -- Why Model Checking Can Improve WCET Analysis -- Regular Model Checking for LTL(MSO) -- Image Computation in Infinite State Model Checking -- Abstract Regular Model Checking -- Global Model-Checking of Infinite-State Systems -- QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings -- Verification of an Advanced mips-Type Out-of-Order Execution Algorithm -- Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values -- Efficient Modeling of Embedded Memories in Bounded Model Checking -- Understanding Counterexamples with explain -- Zapato: Automatic Theorem Proving for Predicate Abstraction Refinement -- JNuke: Efficient Dynamic Analysis for Java -- The HiVy Tool Set -- ObsSlice: A Timed Automata Slicer Based on Observers -- The UCLID Decision Procedure -- MCK: Model Checking the Logic of Knowledge -- Zing: A Model Checker for Concurrent Software -- The Mec 5 Model-Checker -- PlayGame: A Platform for Diagnostic Games -- SAL 2 -- Formal Analysis of Java Programs in JavaFAN -- A Toolset for Modelling and Verification of GALS Systems -- WSAT: A Tool for Formal Analysis of Web Services -- CVC Lite: A New Implementation of the Cooperating Validity Checker -- CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking -- Mechanical Mathematical Methods for Microprocessor Verification. 
650 0 |a Computer science. 
650 0 |a Logic design. 
650 0 |a Software engineering. 
650 0 |a Computers. 
650 0 |a Computer logic. 
650 0 |a Mathematical logic. 
650 0 |a Artificial intelligence. 
650 1 4 |a Computer Science. 
650 2 4 |a Theory of Computation. 
650 2 4 |a Software Engineering. 
650 2 4 |a Logic Design. 
650 2 4 |a Logics and Meanings of Programs. 
650 2 4 |a Mathematical Logic and Formal Languages. 
650 2 4 |a Artificial Intelligence (incl. Robotics). 
700 1 |a Alur, Rajeev.  |e editor. 
700 1 |a Peled, Doron A.  |e editor. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9783540223429 
830 0 |a Lecture Notes in Computer Science,  |x 0302-9743 ;  |v 3114 
856 4 0 |u http://dx.doi.org/10.1007/b98490  |z Full Text via HEAL-Link 
912 |a ZDB-2-SCS 
912 |a ZDB-2-LNC 
912 |a ZDB-2-BAE 
950 |a Computer Science (Springer-11645)