High Performance Embedded Architectures and Compilers First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005. Proceedings /

• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Άλλοι συγγραφείς: Conte, Tom (Επιμελητής έκδοσης), Navarro, Nacho (Επιμελητής έκδοσης), Hwu, Wen-mei W. (Επιμελητής έκδοσης), Valero, Mateo (Επιμελητής έκδοσης), Ungerer, Theo (Επιμελητής έκδοσης)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg, 2005.
• Σειρά: Lecture Notes in Computer Science, 3793
• Θέματα: Computer science.; Arithmetic and logic units, Computer.; Input-output equipment (Computers).; Logic design.; Microprocessors.; Architecture, Computer.; Programming languages (Electronic computers).; Computer Science.; Arithmetic and Logic Structures.; Computer System Implementation.; Programming Languages, Compilers, Interpreters.; Input/Output and Data Communications.; Logic Design.; Processor Architectures.

As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques...

Πίνακας περιεχομένων:

• Invited Program
• Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications
• Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges
• Software Defined Radio – A High Performance Embedded Challenge
• I Analysis and Evaluation Techniques
• A Practical Method for Quickly Evaluating Program Optimizations
• Efficient Sampling Startup for Sampled Processor Simulation
• Enhancing Network Processor Simulation Speed with Statistical Input Sampling
• II Novel Memory and Interconnect Architectures
• Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
• Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
• Streaming Sparse Matrix Compression/Decompression
• XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs
• III Security Architecture
• Memory-Centric Security Architecture
• A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management
• Arc3D: A 3D Obfuscation Architecture
• IV Novel Compiler and Runtime Techniques
• Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations
• Induction Variable Analysis with Delayed Abstractions
• Garbage Collection Hints
• V DomainSpecificArchitectures
• Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors
• Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
• A Single (Unified) Shader GPU Microarchitecture for Embedded Systems
• A Low-Power DSP-Enhanced 32-Bit EISC Processor.