Advances in Computer Systems Architecture 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings /

• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Άλλοι συγγραφείς: Omondi, Amos (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt), Sedukhin, Stanislav (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2003.
• Έκδοση: 1st ed. 2003.
• Σειρά: Lecture Notes in Computer Science, 2823
• Θέματα: Architecture, Computer.; Logic design.; Arithmetic and logic units, Computer.; Input-output equipment (Computers).; Microprocessors.; Computer communication systems.; Computer System Implementation.; Logic Design.; Arithmetic and Logic Structures.; Input/Output and Data Communications.; Processor Architectures.; Computer Communication Networks.

This conference marked the ?rst time that the Asia-Paci?c Computer Systems Architecture Conference was held outside Australasia (i. e. Australia and New Zealand), and was, we hope, the start of what will be a regular event. The conference started in 1992 as a workshop for computer architects in Aust...

Πίνακας περιεχομένων:

• How Can the Earth Simulator Impact on Human Activities
• Toward Architecting and Designing Novel Computers
• Designing Ultra-large Instruction Issue Windows
• Multi-threaded Microprocessors - Evolution or Revolution
• The Development of System Software for Parallel Supercomputers
• Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA
• Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research
• Design and Implementation of Java Processors
• MOOSS: CPU Architecture with Memory Protection and Support for OOP
• Reducing Access Count to Register-Files through Operand Reuse
• SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator
• Towards an Asynchronous MIPS Processor
• On Implementing High Level Concurrency in Java
• Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures
• A Novel Architecture for Genomic Sequence Searching and Alignment
• A Reconfigurable Multi-threaded Architecture Model
• Reconfigurable Instruction-Level Parallel Processor Architecture
• Mapping Applications to a Coarse Grain Reconfigurable System
• Packing with Boundary Constraints for a Reconfigurable Operating System
• Arithmetic Circuits Combining Residue and Signed-Digit Representations
• A New On-the-fly Summation Algorithm
• State Reordering for Low Power Combinational Logic
• User-Level Management of Kernel Memory
• Variable Radix Page Table: A Page Table for Modern Architectures
• L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy
• Legba: Fast Hardware Support for Fine-Grained Protection
• Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem
• Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor
• Performance of the Achilles Router
• Latency Improvement in Virtual Multicasting
• A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks.