Intelligent Memory Systems Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers /

• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Άλλοι συγγραφείς: Chong, Frederic T. (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt), Kozyrakis, Christoforos (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt), Oskin, Mark (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2001.
• Έκδοση: 1st ed. 2001.
• Σειρά: Lecture Notes in Computer Science, 2107
• Θέματα: Artificial intelligence.; Computer engineering.; Computer memory systems.; Computer organization.; Operating systems (Computers).; Computer logic.; Artificial Intelligence.; Computer Engineering.; Memory Structures.; Computer Systems Organization and Communication Networks.; Operating Systems.; Logics and Meanings of Programs.

We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and...

Πίνακας περιεχομένων:

• Memory Technology
• A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
• Software Controlled Reconfigurable On-chip Memory for High Performance Computing
• Processor and Memory Architecture
• Content-Based Prefetching: Initial Results
• Memory System Support for Dynamic Cache Line Assembly
• Adaptively Mapping Code in an Intelligent Memory Architecture
• Applications and Operating Systems
• The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems?
• Memory Management in a PIM-Based Architecture
• Compiler Technology
• Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
• FlexCache: A Framework for Flexible Compiler Generated Data Caching
• Poster Session
• Aggressive Memory-Aware Compilation
• Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips?
• SAGE: A New Analysis and Optimization System for FlexRAM Architecture
• Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
• The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
• Compiler-Directed Cache Line Size Adaptivity ?
• Summary of Question/Answer Sessions for Workshop Presentations.