FME 2002: Formal Methods - Getting IT Right International Symposium of Formal Methods Europe, Copenhagen, Denmark, July 22-24, 2002 Proceedings /

• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Άλλοι συγγραφείς: Eriksson, Lars-Henrik (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt), Lindsay, Peter A. (Επιμελητής έκδοσης, http://id.loc.gov/vocabulary/relators/edt)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2002.
• Έκδοση: 1st ed. 2002.
• Σειρά: Lecture Notes in Computer Science, 2391
• Θέματα: Computer logic.; Software engineering.; Computers.; Programming languages (Electronic computers).; Computer programming.; Logics and Meanings of Programs.; Software Engineering/Programming and Operating Systems.; Theory of Computation.; Software Engineering.; Programming Languages, Compilers, Interpreters.; Programming Techniques.

This volume contains the proceedings of the 2002 symposium Formal Methods th Europe (FME 2002). The symposium was the 11 in a series that began with a VDM Europe symposium in 1987. The symposia are traditionally held every 18 months. In 2002 the symposium was held at the University of Copenhagen, as...

Πίνακας περιεχομένων:

• Little Engines of Proof
• Automated Boundary Testing from Z and B
• Improvements in Coverability Analysis
• Heuristic-Driven Test Case Selection from Formal Specifications. A Case Study
• UniTesK Test Suite Architecture
• Hoare Logic for NanoJava: Auxiliary Variables, Side Effects, and Virtual Methods Revisited
• Do Not Read This
• Safeness of Make-Based Incremental Recompilation
• An Algorithmic Approach to Design Exploration
• Mechanical Abstraction of CSP Z Processes
• Verifying Erlang Code: A Resource Locker Case-Study
• Towards an Integrated Model Checker for Railway Signalling Data
• Correctness by Construction: Integrating Formality into a Commercial Development Process
• VAlloy - Virtual Functions Meet a Relational Language
• Verification Using Test Generation Techniques
• Formal Specification and Static Checking of Gemplus' Electronic Purse Using ESC/Java
• Development of an Embedded Verifier for Java Card Byte Code Using Formal Methods
• Deriving Cryptographically Sound Implementations Using Composition and Formally Verified Bisimulation
• Interference Analysis for Dependable Systems Using Refinement and Abstraction
• The Formal Classification and Verification of Simpson's 4-Slot Asynchronous Communication Mechanism
• Timing Analysis of Assembler Code Control-Flow Paths
• Towards OCL/RT
• On Combining Functional Verification and Performance Evaluation Using CADP
• The Next 700 Synthesis Calculi
• Synthesizing Certified Code
• Refinement in Circus
• Forward Simulation for Data Refinement of Classes
• A Formal Basis for a Program Compilation Proof Tool
• Property Dependent Abstraction of Control Structure for Software Verification
• Closing Open SDL-Systems for Model Checking with DTSpin
• A Generalised Sweep-Line Method for Safety Properties
• Supplementing a UML Development Process with B
• Semantic Web for Extending and Linking Formalisms
• A Language for Describing Wireless Mobile Applications with Dynamic Establishment of Multi-way Synchronization Channels.