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03781nam a22005775i 4500 |
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978-3-540-76650-6 |
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DE-He213 |
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20151204154951.0 |
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100301s2007 gw | s |||| 0|eng d |
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|a 9783540766506
|9 978-3-540-76650-6
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|a 10.1007/978-3-540-76650-6
|2 doi
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|a QA76.758
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|a UMZ
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|a COM051230
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|a 005.1
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|a Formal Methods and Software Engineering
|h [electronic resource] :
|b 9th International Conference on Formal Engineering Methods, ICFEM 2007, Boca Raton, FL, USA, November 14-15, 2007. Proceedings /
|c edited by Michael Butler, Michael G. Hinchey, María M. Larrondo-Petrie.
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg,
|c 2007.
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|a VIII, 387 p.
|b online resource.
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|a text
|b txt
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|a computer
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|a online resource
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|a text file
|b PDF
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|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 4789
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|a Invited Talks -- A System Development Process with Event-B and the Rodin Platform -- Challenges in Software Certification -- Security and Knowledge -- Integrating Formal Methods with System Management -- Formal Engineering of XACML Access Control Policies in VDM++ -- A Verification Framework for Agent Knowledge -- Embedded Systems -- From Model-Based Design to Formal Verification of Adaptive Embedded Systems -- Machine-Assisted Proof Support for Validation Beyond Simulink -- VeSTA: A Tool to Verify the Correct Integration of a Component in a Composite Timed System -- Testing -- Integrating Specification-Based Review and Testing for Detecting Errors in Programs -- Testing for Refinement in CSP -- Reducing Test Sequence Length Using Invertible Sequences -- Automated Analysis -- Model Checking with SAT-Based Characterization of ACTL Formulas -- Automating Refinement Checking in Probabilistic System Design -- Model Checking in Practice: Analysis of Generic Bootloader Using SPIN -- Model Checking Propositional Projection Temporal Logic Based on SPIN -- Hardware -- A Denotational Semantics for Handel-C Hardware Compilation -- Automatic Generation of Verified Concurrent Hardware -- Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking -- Concurrency -- Efficient Symbolic Execution of Large Quantifications in a Process Algebra -- Formalizing SANE Virtual Processor in Thread Algebra -- Calculating and Composing Progress Properties in Terms of the Leads-to Relation -- Erratum -- Erratum to: Challenges in Software Certification.
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|a Computer science.
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|a Software engineering.
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|a Computer programming.
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|a Programming languages (Electronic computers).
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|a Computer logic.
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|a Computers.
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|a Computer Science.
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|a Software Engineering/Programming and Operating Systems.
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|a Programming Techniques.
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|a Software Engineering.
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|a Models and Principles.
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|a Logics and Meanings of Programs.
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|a Programming Languages, Compilers, Interpreters.
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|a Butler, Michael.
|e editor.
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|a Hinchey, Michael G.
|e editor.
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|a Larrondo-Petrie, María M.
|e editor.
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|a SpringerLink (Online service)
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|t Springer eBooks
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|i Printed edition:
|z 9783540766483
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|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 4789
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|u http://dx.doi.org/10.1007/978-3-540-76650-6
|z Full Text via HEAL-Link
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|a ZDB-2-SCS
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|a ZDB-2-LNC
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|a Computer Science (Springer-11645)
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