VLSI-SoC: Design Methodologies for SoC and SiP 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers /

This book contains extended and revised versions of the best papers that were p- sented during the 16th edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 16th conference was held at the Grand Hotel of...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Άλλοι συγγραφείς: Piguet, Christian (Επιμελητής έκδοσης), Reis, Ricardo (Επιμελητής έκδοσης), Soudris, Dimitrios (Επιμελητής έκδοσης)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg, 2010.
Σειρά:IFIP Advances in Information and Communication Technology, 313
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
Πίνακας περιεχομένων:
  • Physical Design Issues in 3-D Integrated Technologies
  • Universal Methodology to Handle Differential Pairs during Pin Assignment
  • Analysis and Design of Charge Pumps for Telecommunication Applications
  • Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems
  • Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process
  • Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs
  • Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study
  • Real-Time Biologically-Inspired Image Exposure Correction
  • A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters
  • On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters
  • Time Efficient Dual-Field Unit for Cryptography-Related Processing
  • A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  • A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
  • Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  • Timing Error Detection and Correction by Time Dilation.