Verification and Validation in Systems Engineering Assessing UML/SysML Design Models /

• Κύριοι συγγραφείς: Debbabi, Mourad (Συγγραφέας), Hassaïne, Fawzi (Συγγραφέας), Jarraya, Yosr (Συγγραφέας), Soeanu, Andrei (Συγγραφέας), Alawneh, Luay (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg, 2010.
• Θέματα: Computer science.; Computer system failures.; Software engineering.; Management information systems.; Computer Science.; Software Engineering/Programming and Operating Systems.; Software Engineering.; System Performance and Evaluation.; Management of Computing and Information Systems.

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be...

Πίνακας περιεχομένων:

• Architecture Frameworks, Model-Driven Architecture, and Simulation
• Unified Modeling Language
• Systems Modeling Language
• Verification, Validation, and Accreditation
• Automatic Approach for Synergistic Verification and Validation
• Software Engineering Metrics in the Context of Systems Engineering
• Verification and Validation of UML Behavioral Diagrams
• Probabilistic Model Checking of SysML Activity Diagrams
• Performance Analysis of Time-Constrained SysML Activity Diagrams
• Semantic Foundations of SysML Activity Diagrams
• Soundness of the Translation Algorithm
• Conclusion.