Verification and Validation in Systems Engineering Assessing UML/SysML Design Models /

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be...

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Bibliographic Details
Main Authors: Debbabi, Mourad (Author), Hassaïne, Fawzi (Author), Jarraya, Yosr (Author), Soeanu, Andrei (Author), Alawneh, Luay (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Berlin, Heidelberg : Springer Berlin Heidelberg, 2010.
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ΒΚΠ - Πατρα: ALFd

Holdings details from ΒΚΠ - Πατρα: ALFd
Call Number: 330.01 BAU
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ΒΚΠ - Πατρα: BSC

Holdings details from ΒΚΠ - Πατρα: BSC
Call Number: 330.01 BAU
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