Verification and Validation in Systems Engineering Assessing UML/SysML Design Models /
Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be...
Main Authors: | , , , , |
---|---|
Corporate Author: | |
Format: | Electronic eBook |
Language: | English |
Published: |
Berlin, Heidelberg :
Springer Berlin Heidelberg,
2010.
|
Subjects: | |
Online Access: | Full Text via HEAL-Link |
Internet
Full Text via HEAL-LinkΒΚΠ - Πατρα: ALFd
Call Number: |
330.01 BAU |
---|---|
Copy 1 | Available |
ΒΚΠ - Πατρα: BSC
Call Number: |
330.01 BAU |
---|---|
Copy 2 | Available |
Copy 3 | Available |