Reconfigurable Computing: Architectures, Tools and Applications 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings /

• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Άλλοι συγγραφείς: Brisk, Philip (Επιμελητής έκδοσης), Figueiredo Coutinho, José Gabriel de (Επιμελητής έκδοσης), Diniz, Pedro C. (Επιμελητής έκδοσης)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2013.
• Σειρά: Lecture Notes in Computer Science, 7806
• Θέματα: Computer science.; Computer hardware.; Computer organization.; Algorithms.; Computer Science.; Computer Hardware.; Computer Systems Organization and Communication Networks.; Algorithm Analysis and Problem Complexity.

 This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing. 

 Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA.