APA (7th ed.) Citation

Taraate, V. (2016). Digital Logic Design Using Verilog: Coding and RTL Synthesis. Springer India : Imprint: Springer.

Chicago Style (17th ed.) Citation

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. New Delhi: Springer India : Imprint: Springer, 2016.

MLA (8th ed.) Citation

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. Springer India : Imprint: Springer, 2016.