Network-on-Chip Architectures A Holistic Design Exploration /
The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning glo...
Main Authors: | , , |
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Corporate Author: | |
Format: | Electronic eBook |
Language: | English |
Published: |
Dordrecht :
Springer Netherlands,
2010.
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Series: | Lecture Notes in Electrical Engineering,
45 |
Subjects: | |
Online Access: | Full Text via HEAL-Link |
Table of Contents:
- MICRO-Architectural Exploration
- A Baseline NoC Architecture
- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]
- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]
- Exploring FaultoTolerant Network-on-Chip Architectures [37]
- On the Effects of Process Variation in Network-on-Chip Architectures [45]
- MACRO-Architectural Exploration
- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]
- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]
- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]
- Digest of Additional NoC MACRO-Architectural Research
- Conclusions and Future Work.