High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

• Main Authors: Wang, Zheng (Author, http://id.loc.gov/vocabulary/relators/aut), Chattopadhyay, Anupam (http://id.loc.gov/vocabulary/relators/aut)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Singapore : Springer Singapore : Imprint: Springer, 2018.
• Edition: 1st ed. 2018.
• Series: Computer Architecture and Design Methodologies,
• Subjects: Electronic circuits.; Computer software-Reusability.; Circuits and Systems.; Performance and Reliability.; Electronic Circuits and Devices.
• Physical Description: XX, 197 p. 104 illus., 72 illus. in color. online resource.
• ISBN: 9789811010736
• ISSN: 2367-3478
• DOI: 10.1007/978-981-10-1073-6

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .