High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

• Κύριοι συγγραφείς: Wang, Zheng (Συγγραφέας, http://id.loc.gov/vocabulary/relators/aut), Chattopadhyay, Anupam (http://id.loc.gov/vocabulary/relators/aut)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Singapore : Springer Singapore : Imprint: Springer, 2018.
• Έκδοση: 1st ed. 2018.
• Σειρά: Computer Architecture and Design Methodologies,
• Θέματα: Electronic circuits.; Computer software-Reusability.; Circuits and Systems.; Performance and Reliability.; Electronic Circuits and Devices.

 This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . 

 Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.