|
|
|
|
LEADER |
02874nam a22005175i 4500 |
001 |
978-981-10-3120-5 |
003 |
DE-He213 |
005 |
20161115075106.0 |
007 |
cr nn 008mamaa |
008 |
161115s2017 si | s |||| 0|eng d |
020 |
|
|
|a 9789811031205
|9 978-981-10-3120-5
|
024 |
7 |
|
|a 10.1007/978-981-10-3120-5
|2 doi
|
040 |
|
|
|d GrThAP
|
050 |
|
4 |
|a Q342
|
072 |
|
7 |
|a UYQ
|2 bicssc
|
072 |
|
7 |
|a COM004000
|2 bisacsh
|
082 |
0 |
4 |
|a 006.3
|2 23
|
100 |
1 |
|
|a Ahmed, Jameel.
|e author.
|
245 |
1 |
0 |
|a Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System
|h [electronic resource] /
|c by Jameel Ahmed, Mohammed Yakoob Siyal, Shaheryar Najam, Zohaib Najam.
|
264 |
|
1 |
|a Singapore :
|b Springer Singapore :
|b Imprint: Springer,
|c 2017.
|
300 |
|
|
|a IX, 62 p. 40 illus., 22 illus. in color.
|b online resource.
|
336 |
|
|
|a text
|b txt
|2 rdacontent
|
337 |
|
|
|a computer
|b c
|2 rdamedia
|
338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
347 |
|
|
|a text file
|b PDF
|2 rda
|
490 |
1 |
|
|a SpringerBriefs in Applied Sciences and Technology,
|x 2191-530X
|
505 |
0 |
|
|a Multiprocessors and Cache Memory -- Energy Delay Product and Throughput -- Challenges and Issues in Modern Computer Architectures -- Real-Time Power And Performance Aware System -- Fuzzy Logic Theory. .
|
520 |
|
|
|a This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors. .
|
650 |
|
0 |
|a Engineering.
|
650 |
|
0 |
|a Microprocessors.
|
650 |
|
0 |
|a Computational intelligence.
|
650 |
|
0 |
|a Electronic circuits.
|
650 |
1 |
4 |
|a Engineering.
|
650 |
2 |
4 |
|a Computational Intelligence.
|
650 |
2 |
4 |
|a Processor Architectures.
|
650 |
2 |
4 |
|a Circuits and Systems.
|
700 |
1 |
|
|a Siyal, Mohammed Yakoob.
|e author.
|
700 |
1 |
|
|a Najam, Shaheryar.
|e author.
|
700 |
1 |
|
|a Najam, Zohaib.
|e author.
|
710 |
2 |
|
|a SpringerLink (Online service)
|
773 |
0 |
|
|t Springer eBooks
|
776 |
0 |
8 |
|i Printed edition:
|z 9789811031199
|
830 |
|
0 |
|a SpringerBriefs in Applied Sciences and Technology,
|x 2191-530X
|
856 |
4 |
0 |
|u http://dx.doi.org/10.1007/978-981-10-3120-5
|z Full Text via HEAL-Link
|
912 |
|
|
|a ZDB-2-ENG
|
950 |
|
|
|a Engineering (Springer-11647)
|