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03983nam a2200577 4500 |
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978-981-13-6362-7 |
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|a 9789811363627
|9 978-981-13-6362-7
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|a 10.1007/978-981-13-6362-7
|2 doi
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|a QA75.5-76.95
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|a TK7885-7895
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|a UK
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|a COM067000
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|a UK
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|a 004
|2 23
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|a Liu, Leibo.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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|a Massive MIMO Detection Algorithm and VLSI Architecture
|h [electronic resource] /
|c by Leibo Liu, Guiqiang Peng, Shaojun Wei.
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|a 1st ed. 2019.
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|a Singapore :
|b Springer Singapore :
|b Imprint: Springer,
|c 2019.
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|a XVI, 336 p. 186 illus., 120 illus. in color.
|b online resource.
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|a text
|b txt
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|a computer
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|2 rdamedia
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|a online resource
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|a text file
|b PDF
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|a Chapter 1 Introduction -- Chapter 2 Linear Massive MIMO Detection Algorithm -- Chapter 3 Architecture of Linear Massive MIMO Detection -- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm -- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection -- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection -- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
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|a This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method. .
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|a Computer hardware.
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|a Electronic circuits.
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|a Computer engineering.
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|a Wireless communication systems.
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|a Mobile communication systems.
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|a Information theory.
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|a Computer Hardware.
|0 http://scigraph.springernature.com/things/product-market-codes/I1200X
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|a Circuits and Systems.
|0 http://scigraph.springernature.com/things/product-market-codes/T24068
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|a Computer Engineering.
|0 http://scigraph.springernature.com/things/product-market-codes/I27000
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|a Wireless and Mobile Communication.
|0 http://scigraph.springernature.com/things/product-market-codes/T24100
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|a Information and Communication, Circuits.
|0 http://scigraph.springernature.com/things/product-market-codes/M13038
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1 |
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|a Peng, Guiqiang.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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1 |
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|a Wei, Shaojun.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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|a SpringerLink (Online service)
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|t Springer eBooks
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|i Printed edition:
|z 9789811363610
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|i Printed edition:
|z 9789811363634
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|i Printed edition:
|z 9789811363641
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|u https://doi.org/10.1007/978-981-13-6362-7
|z Full Text via HEAL-Link
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|a ZDB-2-SCS
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950 |
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|a Computer Science (Springer-11645)
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