Iterative decoding techniques on digital receivers

• Κύριος συγγραφέας: Κάνιστρας, Νικόλαος
• Άλλοι συγγραφείς: Παλιουράς, Βασίλειος
• Μορφή: Thesis
• Γλώσσα: English
• Έκδοση: 2017
• Θέματα: Forward error correction (FEC); Ehannel coding; Low-density parity-check (LDPC) codes; Iterative decoding; Message-passing decoding; Density evolution technique; Πρόσθια διόρθωση σφαλμάτων (FEC); Κωδικοποίηση καναλιού; Κώδικες χαμηλής πυκνότητας πίνακα ελέγχου ισοτιμίας (LDPC); Επαναληπτική αποκωδικοποίηση; Αποκωδικοποίηση μέσω ανταλλαγής μηνυμάτων; Τεχνική εξέλιξης κατανομονών; 004.6

The Industrial Revolution that was accomplished during the 19th century has been followed by the Information Revolution that took place during the century coming after. The 21st century came with an explosion in information diffusion. “Information explosion (Info-plosion) is one of the most substantial phenomena in 21st century. Not only the mentions in blogs and twitter, but also the data from various kinds of sensors is becoming to explode considerably”. Info-plosion has substantially increased the requirements for the reliable and efficient transmission of information. Consequently, methods and techniques that ensure reliable, safe and fast transmission of information are becoming more and more essential. Digital Communications, Information Theory, and Error Correction Codes are the main research areas that study how to achieve such a goal. Many error correction codes have been presented in the past, but in recent years a class of codes has imposed itself as the best candidate to provide transmission rates close to the Shannon’s theoretical limit, namely Low Density Parity Check (LDPC) codes. LDPC codes are a class of codes that can achieve reliable communication while keeping the complexity of the encoder and decoder implementation controllable. The performances of LDPC codes have been shown to be very close to the theoretical limit that a code can reach in a given channel, the channel capacity. However, implementation of LDPC-based systems of very good performance and at the same time, very low complexity, remains a challenge. There is always a need for smaller and faster communication devices with low power consumption and low cost, as a consequence, error correction modules must be improved to meet these specifications covering at the same time all required functionalities. This thesis investigates techniques for efficient design of LDPC decoders, relaxing the need for traditional time-consuming simulations. The main focus of the thesis is on developing reliable models that can predict with high accuracy the decoding performance for particular implementations of LDPC decoders. Since unlimited LDPC codes can be constructed and used, in combination with a variety of decoding algorithms, such a model must be parameterized in terms of the implemented code and the decoding algorithm. Moreover, the estimation model must take into account the specific accuracy implemented by the decoder.