Static random access memories via hardware cell libraries : an emphasis on their structure and writing function

• Κύριος συγγραφέας: Σιμόπουλος, Θεόδωρος
• Άλλοι συγγραφείς: Αλεξίου, Γεώργιος
• Μορφή: Thesis
• Γλώσσα: English
• Έκδοση: 2017
• Θέματα: SRAM; WDSRAM; Write function; Speed-up; Power driver; Memory write via multi voltage supply levels; New precharge scheme; Multi field SRAM access; Intra-encoders; SRAM fields; Στατική μνήμη τυχαίας προσπέλασης; Διαδικασία εγγραφής; Επιτάχυνση; Οδηγός τάσεων εγγραφής; Εγγραφή μνήμης μέσω πολλαπλών τάσεων τροφοδοσίας; Νέο σχήμα προ-φόρτισης; Μνήμη προσπέλασης πολλαπλών πεδίων; Ενδο-κωδικοποιητές; Πεδία στατικής μνήμης; 004.53

Mankind came across the need of storing data, either as intermediate or terminal results, from its early stages. First, with the use of non-electronic and non-mechanical devices with major representative the tallies, as they are called, even before the invention of writing. Later, the use of punched cards which were fed to mechanical computational systems was found helpful. However, storage devices met a tremendous progress during the information age which, in turn, was also helped by the storage devices to evolve rapidly. A few years later we were led to the formation of the 6T electronic storage element which is in wide use even in nowadays. The device miniaturization, surpassing to the submicron dimensions, equipped computer systems with cache memories of capacity several megabytes, helping the increase of the computational power. In this dissertation, at first, a logic sequence of inventions that concern computer memory, is presented, until we reach the memory systems that are in use in nowadays. The benefits in the use of hardware cell libraries, which can extend the research in the memory field with implementations that are beyond the typical, are expressed and compared to the memory compiler tools which automate the memory production procedure. In order to support this dissertation, two hardware libraries have been developed from scratch. One that includes standard cells and one that includes memory cells. Both implemented on the same UMC 65 nm technology process. Via the use of these libraries an innovative static memory implementation which speeds-up the writing function up to three times is proposed. This new memory is named WDSRAM. The dissertation continues with a background research knowledge concerning the static memory field. The basic structure, that the Static Random Access Memories support, is presented and different implementations of the SRAM storage cells are explained. The typical 6T SRAM cell model is discussed in detail, with reference to its three operational states, which are the cell read operation, the cell write operation and the data retain operation. Furthermore, the circuitry, that supports the storage cell’s operation states, is shown at its possible variations. This circuitry concerns the Bit Line prechargers, which is also referred as the memory’s conditioning circuitry, the sense amplifiers and the write drivers. For the support of this dissertation, the hybrid – modern variation of the precharger, the pmos cross – coupled sense amplifier and the pass gates style write driver are chosen. The background research knowledge concludes with the presentation of the memory’s periphery circuitry, which involves the row and the column decoder and the memory controller. The row decoder is used to decode the address, while the column decoder is used to decode the memory’s page. The standard cell library, that is implemented, is called Ceid Standard Cell Library and is a complete hardware library including combinational cells, sequential cells and other support cells like logic level tiers and area fillers. All cells support 6 views, from behavioral description view to parasitics layout extraction view and most of the cells exist in three driving strengths. With these cells, ASIC designs can be implemented, starting from any level of abstraction in the circuitry design methodology. All the library’s cells are area, timing, power and functionally characterized and therefore, related reports are able of being produced, when synthesizing designs on cells of this library from EDA tools. The guidelines that were followed in order to implement the combinational, sequential and support cells are explained in detail. The cells that the library includes are enumerated along with the function they support. The horizontal and vertical abutment of the cells is also presented. This standard cell library was used to describe the memory’s periphery circuitry, during my dissertation. Each of the periphery circuitry is treated as macro-cell, following the methodology of macro-cell creation that is also presented. However, the Ceid Standard Cell Library can also be used as a typical hardware cell library in order to implement any ASIC design. Though memory compilers can produce static memory designs rapidly, these designs are flattened in the material layout level, minimizing the ability of researching on the structural elements of the memory as any modifications would have to be repeated to each presence of the memory’s microstructure in the need to complete the whole design. On the other hand, with the use of memory hardware libraries, the design of the memory is done in cell level, resulting to a memory that is a collection of selectable cells abutted together. Therefore, modifying one cell of the memory, also modifies all the other instances of this cell inside the memory. For this reason, during my dissertation it was essential to implement a static memory library so as to help my research evolve in the memory’s structural elements. This library is called Ceid Memory Library and is a complete library including all the basic cells via which static memory designs can be created. The library is based on the 6T typical storage cell model, the Hybrid – Modern precharger implementation with equalization which has both nmos and pmos precharge units, the pmos cross-coupled sense amplifier for the read function and the pass gates style driver for the writing function. These basic cells are presented and the first two of them have been altered in order to support the WDSRAM. An innovative memory that is proposed and rapidly writes the storage cells with a speed-up factor of three in accordance with the typical implementation model. Besides the basic memory cells, the Ceid Memory Library also comprises of support cells that can be used as predecoders, area fillers and wire line extenders. Moreover, typical static memory circuits of variable size have been implemented using the cells of this library. These circuits are presented and are used not only to verify the proper operation of the library but also to support the enhancements on the WDSRAM’s write function. The memory cells are enumerated and the memory grid structure that the library supports is presented and explained. The Ceid Memory Library and the Ceid Standard Cell Library are available online from the Ceid’s VLSI Lab web site. The WDSRAM is a new static random access memory that speeds-up the writing function of the storage cells up to three times. This is achieved via multi voltage manipulation on the memory’s storage cells that form the memory’s word, along with a different Bit Line precharge scheme. Furthermore, though not necessary, the multi voltages are generated internally by the memory. In order to support this innovative memory, new memory cells had to be created. The first is the Row Power Driver, as it is called, which has the role of altering the voltage levels that the transistors of the storage cells see during their writing procedure. The Row Power Driver consists of three parts. The voltage divider, the signal switcher and the output normalizer. All parts are explained in detail. The second is the Bit Line Precharger which supports the WDSRAM’s new precharge scheme, with the Bit Lines diverging and converging from a central voltage level operating point. The new Bit Line precharger cell is presented in schematic and material layout levels and its behavior is shown in comparison with the precharge function of the typical static memory model. Minor modifications have been performed to the Ceid Memory Library’s 6T storage cell in order to accept the power scheme from the Row Power Driver. The behavior of all these cells is presented and analyzed. Furthermore, the abutment of these new and modified cells is described and the connections that are created between then, are shown. The proper operation and the write function speed-up of the WDSRAM is verified via a simulation process called Virtual Variable Size which simulates memories as if they were of bigger size. This process is explained in detail and it was essential to be used in order to have first results of the WDSRAM’s performance due to the time-consuming material layout design and time-taking simulation of the big memory test circuits, as all test have been performed in the parasitics extraction level. Furthermore, the operation of the WDSRAM and the maintenance of the memory’s write function speed-up gain is verified for different FEOL process models in accordance with different temperature operating points. The results are presented. In order to verify the WDSRAM’s speed-up gain in real sized memories, a hardware procedure is stated, via which the creation of WDSRAMs of any size is possible. This procedure uses a hierarchical architectural scheme based on a WDSRAM sector. WDSRAMs of any size can be created using this architectural scheme, which was chosen, as the speed-up gain is inherited to the whole memory via hierarchy, starting from a WDSRAM sector. For the test circuits, the WDSRAM sector is defined to be of size 256x8 bits and its implementation is presented in schematic and layout models, analyzing it in detail. This sector is simulated and compared with the typical 256x8 bit SRAM model and the maintenance of the WDSRAM’s speed-up gain is confirmed in the sector level. With the abutment of this sector a 1Kx32 bit WDSRAM has been implemented in schematic and material layout models. These models are explained in detail, starting with the creation of the memory rows, leading to the formation of the double-rows, between every pair of which, the I/O tunnel is present. The power scheme of the 1Kx32 bit WDSRAM, which is essential in order to uniformly provide the power supply to the memory’s Row Power Driver that each sector makes use of, is discussed/analyzed. The 1Kx32 bit WDSRAM is simulated against the typical implementation model of the same size and configuration. The simulation process is explained in detail and the simulation results confirm that the WDSRAM’s rapid write function evolves on bigger memories as the speed-up gain of its write function has remained against the typical implementation model. This dissertation concludes with the presentation of memory design which reveals the advantages of the use of hardware cell libraries when creating memories and extends the research on the static memory field beyond the typical. A new static memory enabling and accessing scheme is defined, which allows the simultaneous reading or writing of memory portions, which are called fields and can be present even inside the same memory page. This is succeeded with the use of special intra-encoders that are adjacent to each memory field and a double decoding scheme. The intra-encoders are explained in its schematic and material layout views. The formation of these intra-encoders relied on their characteristic of being the most automated ones, in concern of the material layout implementation of this innovative memory. Indeed, the intra-encoders can be iterated as they are, from field to field, during the creation of the layout of the memory supporting the variability of their function on the metal via placement procedure, which can be automated using tool command language. This memory is called Multi-Field Accessing Memory. The addressing of the Multi-Field Accessing Memory is described and the usage of the double decoder scheme is shown, which, in brief, is responsible for the address and the field decoding. To support the decoding scheme of this multi-field memory, an 8T storage cell, which has a pair of accessing transistors at each side of the Bit Lines, is defined and presented at its implemented in schematic and material layout level. The behavior of this cell is also illustrated. At the end, the simulation results of a multi-field SRAM test circuit are presented, which verify the successful multi-accessing procedure of the memory. The test circuit, that was used for this verification, comprises of four rows of fields and four columns of fields with each field being a sum of 8x8 storage cells. The test results confirm the correct operation of the multi-field SRAM, with the simultaneous addressing and accessing of the memory fields.