| Περίληψη: | This MSc Thesis deals with a novel concept that suggests a new way of constructing
a fractional-order differentiator/integrator. This approach offers several benefits, with
the most important being the apparent reduced spread of time-constants and scaling
factors. This leads into differentiator/integrator realizations with capability for
implementation in fully integrated form.
The approximations of fractional-order differentiator/integrator transfer functions
are currently performed using integer-order rational functions, which are in general
implemented through appropriate multi-feedback topologies. The spread of the values
of time-constants as well of scaling factors in these topologies increase as the order
of the differentiator/integrator and/or the order of the approximation increases. This
could lead to non-practical values of capacitances and resistances/transconductances
needed for the implementation. A possible solution to overcome this obstacle is introduced
in this thesis and is based on the employment of a combination of fractionaland
integer-order integrators and differentiators for implementing the desired function.
The main concept is to construct a fractional-order integrator/differentiator that, even
for high orders, will present low values of spreads. This could be achieved by combining
a fractional-order part of low order with an integer-order part, a connection
that leads to the implementation of a fractional-order integrator/differentiator of high
order. Two methods of approximation are used for this purpose; 2nd− to 5th− order
Continued Fraction Expansion and 3rd− and 5th− order of Oustaloup approximation.
The performance of the proposed scheme is verified through post-layout simulations
using Cadence and the Design Kit provided by the Austria Mikro Systems (AMS)
0.35μm CMOS technology process.
|
|---|
