VLSI architectures for error correction in digital communication systems

• Κύριος συγγραφέας: Τσατσαράγκος, Ιωάννης
• Άλλοι συγγραφείς: Παλιουράς, Βασίλης
• Μορφή: Thesis
• Γλώσσα: English
• Έκδοση: 2019
• Θέματα: Forward error correction (FEC); Channel decoder; Llow-density parity-check (LDPC) codes; Iterative decoding; WiFi; WiMAX; Error floor; Min-Sum decoding algorithm; Interconnection network; Message-passing decoding; Πρόσθια διόρθωση σφαλμάτων (FEC); Αποκωδικοποιητής καναλιού; Επαναληπτική αποκωδικοποίηση; Κώδικες χαμηλής πυκνότητας πίνακα ελέγχου ισοτιμίας (LDPC); Αλγόριθμος αποκωδικοποίησης Min-Sum; Δίκτυο διασύνδεσης; Αποκωδικοποίηση μέσω ανταλλαγής μηνυμάτων; 005.717

During the last decades, the deployment of large, high-speed data networks for the exchange, processing, and storage of digital information has further enhanced an ever increasing need for effective and reliable digital communication and data storage systems. An important issue related to the design and operation of such systems is the error correction that ensures error-free communication during data transmission. Many communication channels are subject to channel noise, and thus errors may be introduced during transmission. Information theory and coding theory introduce error-correcting techniques that enable reliable delivery of digital data over unreliable communication channels. Low-density parity-check (LDPC) codes are a subcategory of linear block error correction codes, which show excellent error-correcting performance with moderate decoding complexity. LDPC codes have been considered for adoption in several industrial standards for next-generation communication systems, such as DVB-S2, ITU-T G.hn, 10GBASE-T, WiMAX, and WiFi. The main challenge when designing an LDPC-based system is the implementation of decoder architectures that efficiently manage the requirement for good error-correcting performance, high speed, low complexity and power consumption. A drawback of LDPC codes is that they suffer from the error floor, i.e., a region in the bit error rate (BER) vs. noise level plot where BER reduction slows down as the noise level decreases. Current research efforts target to the improvement of LDPC codes, by devising new code construction methods and efficient decoding algorithms. This thesis focuses on the development of effective forward error correction (FEC) algorithms, and the design and implementation of efficient LDPC decoder architectures. Several techniques have been studied in order to improve the decoding performance, especially in the error floor region of operation. Crucial design parameters to be optimally jointly defined are the structure of the LDPC code, the iterative decoding algorithm, and the data quantization scheme. Moreover, hardware-efficient, high-speed LDPC decoder architectures were implemented, in order to satisfy the strict latency and area constraints, imposed by the modern communication standards.