Design of fractional-order controller for two interacting tank level

In this M.Sc. Thesis, a fractional-order Proportional-Integral (PI) controller for a two interacting tank level system is designed. The proposed concept offers the benefit of using a single topology for the varying operating behavior of this application. In addition, the final circuit comprises a co...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Μπιζώνης, Βασίλειος
Άλλοι συγγραφείς: Ψυχαλίνος, Κώστας
Μορφή: Thesis
Γλώσσα:English
Έκδοση: 2019
Θέματα:
Διαθέσιμο Online:http://hdl.handle.net/10889/12540
Περιγραφή
Περίληψη:In this M.Sc. Thesis, a fractional-order Proportional-Integral (PI) controller for a two interacting tank level system is designed. The proposed concept offers the benefit of using a single topology for the varying operating behavior of this application. In addition, the final circuit comprises a compact solution with low power dissipation and reduced count of active components. The actual purpose of the controller is the adjustment of the liquid level of one tank, by varying the inflow rate of the other tank with a control valve. The transfer function that describes the operation of the system and, consequently, this of the required fractional PI controller vary, depending on the liquid level of the two tanks. This raises the necessity of a topology with tunable parameters. The integral stage of this controller, of which the fractional order remains constant in each case, is implemented using an RC network and an integrator circuit. This implementation, as well as the fact that the controller sub-circuits are current mirrors and trans-linear topologies, lead to a simpler final circuit with reduced amount of components. The gains, as well as the time constant, are electronically tunable, adjusting, therefore, the transfer function of the controller to the system operation. This offers the capability of using the same topology for the multiple operating regions. Moreover, the transistors of all topologies are selected to operate in weak inversion, this way, reducing the overall power dissipation and offering linear tuning. The performance of the proposed scheme is verified through post-layout simulations using Cadence and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35µm CMOS technology process.