| Περίληψη: | The increasing demand for higher data rates and for more connected devices has led
to Massive MIMO Technology. Having a high number of antennas is the basic feature
of Massive MIMO networks and this is what differentiates them from conventional
MIMO systems where users are served from base-stations with a small number of
antennas. Massive MIMO technology has many benefits such as high link reliability,
high throughput rate, high spectral efficiency and for this reason it will play a crucial
role at 5G networks in the future. However due to large number of antennas, Massive
MIMO systems are known for their cost and for their high computational complexity.
Maximum-Likelihood (ML) detector yields the optimal solution in MIMO detec-
tion problem but its complexity is susceptible to high-order modulation schemes and
to large-scale systems. Sphere Decoder (SD) provides a good bit error rate (BER)
performance similar to ML detector with the advantage that the complexity of SD is
polynomial in contrast with ML-detector’s complexity which rises exponentially with
the number of transmit and receive antennas. SD intends to detect the transmitted sig-
nal vector by searching only the candidate vectors which lie inside a hypersphere with
radius R 0 around the received signal r in contrast with ML detector where all candidate
vectors are examined. The method employed to calculate IR has a critical impact on
the complexity of SD. A large initial value of sphere radius can lead to an exhaustive
search between numerous possible transmitted symbols, while in contrast a very small
radius may contain no lattice point inside the sphere and the search will have to be
restarted with a new estimation of IR.
In this thesis, an implementation of a SD in a Massive MIMO network is pre-
sented. This thesis focuses on uplink communication where users transmit data to the
base-station. Furthermore a comparison between SD and other detectors, proposed in
the literature, is presented based on BER performance using MATLAB simulations.
Various methods of calculating IR are evaluated in this thesis considering the compu-
tational complexity, the latency, the required wordlength for hardware implementation
and the number of visited nodes during detection, which implies execution time and
power consumption of the method. Implementation results of these methods are also
evaluated. An effective method for calculating IR is proposed. Finally, a hardware
implementation of SD targeting FPGA designs is recommended.
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