Data representation and adder architectures in the presence of variations

• Κύριος συγγραφέας: Παπαχατζόπουλος, Κλεάνθης
• Άλλοι συγγραφείς: Παλιουράς, Βασίλειος
• Μορφή: Thesis
• Γλώσσα: English
• Έκδοση: 2019
• Θέματα: Arithmetic circuits; VLSI; Variation-tolerant design; Adder architectures; Αριθμητικά κυκλώματα; Διακυμάνσεις παραμέτρων; Αθροιστές; 621.395

It is well known that reduced logic depth allows for operation at low voltages, therefore reducing power dissipation. However, such circuits are particularly susceptible to variations, which may compromise expected benefits. This Master Thesis is focused on the evaluation of the performance and power character- istics of certain adder structures under inter- and intra-die process variations in deep-submicron technology nodes. Specifically, it presents a solution for low-power addition under variability, which successfully handles the challenge of increased threshold voltage variation. We quanti- tatively compare the impact of variation on the performance of Ripple-Carry Adder (RCA) and Borrow-Save Adder (BSA), and quantify the average power reduction achieved by BSA attained at low voltage values, at the cost of increased delay variation. In addition, we propose a tech- nique that enhances BSA tolerance to variations. Using Statistical SPICE Timing Evaluation at 45-nm, 32-nm, and 16-nm nodes, we estimate the maximum critical path delay variation and average power dissipation of BSA at different supply voltages. Our analysis reveals that BSA achieves three times smaller standard deviation of maximum delay than RCA at the same supply voltage for a 45-nm technology node. In addition, we show that it is possible to substantially reduce the supply voltage, decreasing by almost 60% the overall power dissipation of BSA in comparison to a counterpart operating at nominal voltage, while keeping maximum delay less than that of RCA. Furthermore, simple design optimizations in the design of BSA are intro- duced that trade latency for variability, significantly reducing normalized standard deviation of the maximum delay. BSIM 4 MOSFET libraries have been employed for a precise evaluation of performance-power characteristics in todays technology nodes. Furthermore, this Master Thesis introduces two statistical delay-variability models for RCA and BSA. The models consider both intra- and inter-die delay variations. The first proposed model, named as Type-I model, is derived in the form of expressions for the computation of the exact Probability Density Functions (PDFs) of maximum output delays of the two adder archi- tectures. Furthermore, closed formulas for the correlation coefficients between output delays of the aforementioned adder architectures are presented. The introduced derived correlation coef- ficients are subsequently combined with Clark’s method to derive the second proposed model, Type-II model, which comprises approximations of the maximum delay PDFs of RCA and BSA. The proposed Clark-based Type-II model uses Gaussian distributions to approximate maximum delay distributions, taking into account the correlation between logic paths. Simulation results and the derived exact Type-I PDFs are found to perfectly agree, while the proposed Clark-based Type-II models present an error for standard deviation of maximum delay that increases as BSA word length increases. Both the introduced models and the simulations prove that BSAs achieve narrower delay distributions than RCAs, i.e., they significantly reduce delay variance. Conse- quently, BSAs are proven to be suitable for variation-tolerant applications by providing a timing safety margin, when compared to RCA architectures. The underlying analysis indicates that, for the case of BSA and (inter- and) intra-die delay variations, the Type-II models introduce no-negligible errors, which are as much as 16% of the standard deviation of maximum delay for a 256-bit BSA, as the Type-II Gaussian PDF approximations deviate significantly from the exact Type-I PDFs. However, for all RCA and BSA inter-die only variation cases, both Types present satisfactory accuracy due to Gaussian shape of exact PDFs.