Data representation and adder architectures in the presence of variations

• Main Author: Παπαχατζόπουλος, Κλεάνθης
• Other Authors: Παλιουράς, Βασίλειος
• Format: Thesis
• Language: English
• Published: 2019
• Subjects: Arithmetic circuits; VLSI; Variation-tolerant design; Adder architectures; Αριθμητικά κυκλώματα; Διακυμάνσεις παραμέτρων; Αθροιστές; 621.395

It is well known that reduced logic depth allows for operation at low voltages, therefore reducing power dissipation. However, such circuits are particularly susceptible to variations, which may compromise expected benefits. This Master Thesis is focused on the evaluation of the performance and p...