Hardware for deep learning
The purpose of this diploma thesis is the research and development of efficient hardware architecture which can be used as an accelerator for Neural Networks of Deep Learning. More specifically, the development of the circuit was carried out with hardware description language (VHDL) and high-level,...
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| Διαθέσιμο Online: | http://hdl.handle.net/10889/12974 |
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nemertes-10889-129742022-09-05T20:25:42Z Hardware for deep learning Αρχιτεκτονικές υλικού για deep learning Ζαρκαδούλα, Καλλιρρόη Παλιουράς, Βασίλειος Θεοδωρίδης, Γεώργιος Zarkadoula, Kallirroi Deep learning Accelerators Eπιταχυντές Νευρωνικά δίκτυα The purpose of this diploma thesis is the research and development of efficient hardware architecture which can be used as an accelerator for Neural Networks of Deep Learning. More specifically, the development of the circuit was carried out with hardware description language (VHDL) and high-level, general-purpose programming language Python for the implementation of the designed architecture through Tensorflow, which is an open-source software library. Further research and optimization were conducted mainly focusing on delay and accuracy loss taking into consideration the size of the network, the scalability, and processing of the data input as well as the training rate of the Neural Network. Σκοπός της παρούσας διπλωματικής εργασίας είναι η έρευνα και η ανάπτυξη κατάλληλου υλικού (hardware) το οποίο πρόκειται να χρησιμοποιηθεί ως επιταχυντής (accelerator) σε Νευρωνικά Δίκτυα του Deep Learning. Πιο συγκεκριμένα, για την ανάπτυξη του συστήματος χρησιμοποιήθηκαν μέθοδοι προγραμματισμού σε επίπεδο περιγραφής υλικού (συγκεκριμένα VHDL) αλλά και η γλώσσα προγραμματισμού Python για την υλοποίηση του συστήματος μέσω της βιβλιοθήκης ανοιχτού κώδικα του Tensorflow. Περαιτέρω μελέτη και βελτιστοποίηση έγινε με κύριο άξονα την καθυστέρη και την ακρίβεια με παράμετρο το μέγεθος του δικτύου, την τμηματοποίηση και την επεξεργασία των δεδομένων εισόδου καθώς και το ρυθμό εκπαίδευσης του Νευρωνικού Δικτύου. 2020-01-16T20:33:54Z 2020-01-16T20:33:54Z 2019-10-22 Thesis http://hdl.handle.net/10889/12974 en 0 application/pdf |
| institution |
UPatras |
| collection |
Nemertes |
| language |
English |
| topic |
Deep learning Accelerators Eπιταχυντές Νευρωνικά δίκτυα |
| spellingShingle |
Deep learning Accelerators Eπιταχυντές Νευρωνικά δίκτυα Ζαρκαδούλα, Καλλιρρόη Hardware for deep learning |
| description |
The purpose of this diploma thesis is the research and development of efficient hardware architecture which can be used as an accelerator for Neural Networks of Deep Learning. More specifically, the development of the circuit was carried out with hardware description language (VHDL) and high-level, general-purpose programming language Python for the implementation of the designed architecture through Tensorflow, which is an open-source software library. Further research and optimization were conducted mainly focusing on delay and accuracy loss taking into consideration the size of the network, the scalability, and processing of the data input as well as the training rate of the Neural Network. |
| author2 |
Παλιουράς, Βασίλειος |
| author_facet |
Παλιουράς, Βασίλειος Ζαρκαδούλα, Καλλιρρόη |
| format |
Thesis |
| author |
Ζαρκαδούλα, Καλλιρρόη |
| author_sort |
Ζαρκαδούλα, Καλλιρρόη |
| title |
Hardware for deep learning |
| title_short |
Hardware for deep learning |
| title_full |
Hardware for deep learning |
| title_fullStr |
Hardware for deep learning |
| title_full_unstemmed |
Hardware for deep learning |
| title_sort |
hardware for deep learning |
| publishDate |
2020 |
| url |
http://hdl.handle.net/10889/12974 |
| work_keys_str_mv |
AT zarkadoulakallirroē hardwarefordeeplearning AT zarkadoulakallirroē architektonikesylikougiadeeplearning |
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