Design and implementation of an FPGA based TDC with picosecond level resolution

This thesis deals with the design and implementation of an FPGA based time to digital converter by employing a tapped delay line. Several issues regarding the implementation that are dealt with include clock skew, jitter and non linearity. A down-sampling ap- proach is proposed in order to improv...

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Κύριος συγγραφέας:	Δικόπουλος, Ευάγγελος
Άλλοι συγγραφείς:	Μπίρμπας, Αλέξιος
Μορφή:	Thesis
Γλώσσα:	English
Έκδοση:	2020
Θέματα:	Time to digital converter Data converters Field Programmable Gate Array (FPGA) Mixed signal Jitter Integrated circuit Μετατροπείς δεδομένων Επεξεργασία σημάτων
Διαθέσιμο Online:	http://hdl.handle.net/10889/12988

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spelling	nemertes-10889-129882022-09-05T14:05:22Z Design and implementation of an FPGA based TDC with picosecond level resolution Σχεδιασμός και υλοποίηση ενός TDC σε πλατφόρμα FPGA με ακρίβεια επιπέδου picosecond Δικόπουλος, Ευάγγελος Μπίρμπας, Αλέξιος Μπίρμπας, Αλέξιος Μπίρμπας, Mιχάλης Dikopoulos, Evangelos Time to digital converter Data converters Field Programmable Gate Array (FPGA) Mixed signal Jitter Integrated circuit Μετατροπείς δεδομένων Επεξεργασία σημάτων This thesis deals with the design and implementation of an FPGA based time to digital converter by employing a tapped delay line. Several issues regarding the implementation that are dealt with include clock skew, jitter and non linearity. A down-sampling ap- proach is proposed in order to improve the performance of the TDC, while the converter is characterised by a timing experiment that uses clock signals provided by the FPGA clock manager. While the trade-o s regarding the various operation modes are being presented, this thesis also discusses the theory of time to digital converters as well as various circuit implementations. Finally, we also discuss the advantages of TDCs, when taking into account technology scaling, as well as the processing of signals in the time domain. Αυτή η εργασία ασχολείται με τον σχεδιασμό και την υλοποίηση ενός TDC σε πλατφόρμα FPGA με την χρήση της μεθόδου tapped delay-line. Αναλύονται και προτείνονται λύσεις για διάφορα προβλήματα σχετικά με την υλοποίηση του converter σε FPGA, συμπεριλαμβανομένου ζητήματα σχετικά με το clock skew, το jitter και την γραμμικότητα. Προτείνουμε μια μέθοδο down-sampling για την βελτίωση της απόδοσης του TDC, ενώ παρουσιάζουμε τα πειράματα χρονισμού που διεξήχθησαν για τον χαρακτηρισμό του συστήματος. Ενώ παρουσιάζουμε τα trade-offs σχετικά με τους διάφορους τρόπους λειτουργίας του TDC, αυτή η διατριβή ασχολείται επίσης με την θεωρία των TDCs καθώς και με τις διάφορες κυκλωματικές υλοποιήσεις αυτών. Τέλος, παρουσιάζουμε τα πλεονεκτήματα των TDCs, σχετικά με την κλιμάκωση των μεγεθών των MOS τρανζίστορ, καθώς και την επεξεργασία σημάτων στο πεδίο του χρόνου. 2020-01-16T20:43:05Z 2020-01-16T20:43:05Z 2019-10-09 Thesis http://hdl.handle.net/10889/12988 en 0 application/pdf
institution	UPatras
collection	Nemertes
language	English
topic	Time to digital converter Data converters Field Programmable Gate Array (FPGA) Mixed signal Jitter Integrated circuit Μετατροπείς δεδομένων Επεξεργασία σημάτων
spellingShingle	Time to digital converter Data converters Field Programmable Gate Array (FPGA) Mixed signal Jitter Integrated circuit Μετατροπείς δεδομένων Επεξεργασία σημάτων Δικόπουλος, Ευάγγελος Design and implementation of an FPGA based TDC with picosecond level resolution
description	This thesis deals with the design and implementation of an FPGA based time to digital converter by employing a tapped delay line. Several issues regarding the implementation that are dealt with include clock skew, jitter and non linearity. A down-sampling ap- proach is proposed in order to improve the performance of the TDC, while the converter is characterised by a timing experiment that uses clock signals provided by the FPGA clock manager. While the trade-o s regarding the various operation modes are being presented, this thesis also discusses the theory of time to digital converters as well as various circuit implementations. Finally, we also discuss the advantages of TDCs, when taking into account technology scaling, as well as the processing of signals in the time domain.
author2	Μπίρμπας, Αλέξιος
author_facet	Μπίρμπας, Αλέξιος Δικόπουλος, Ευάγγελος
format	Thesis
author	Δικόπουλος, Ευάγγελος
author_sort	Δικόπουλος, Ευάγγελος
title	Design and implementation of an FPGA based TDC with picosecond level resolution
title_short	Design and implementation of an FPGA based TDC with picosecond level resolution
title_full	Design and implementation of an FPGA based TDC with picosecond level resolution
title_fullStr	Design and implementation of an FPGA based TDC with picosecond level resolution
title_full_unstemmed	Design and implementation of an FPGA based TDC with picosecond level resolution
title_sort	design and implementation of an fpga based tdc with picosecond level resolution
publishDate	2020
url	http://hdl.handle.net/10889/12988
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Design and implementation of an FPGA based TDC with picosecond level resolution

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