Design and implementation of an FPGA based TDC with picosecond level resolution

• Κύριος συγγραφέας: Δικόπουλος, Ευάγγελος
• Άλλοι συγγραφείς: Μπίρμπας, Αλέξιος
• Μορφή: Thesis
• Γλώσσα: English
• Έκδοση: 2020
• Θέματα: Time to digital converter; Data converters; Field Programmable Gate Array (FPGA); Mixed signal; Jitter; Integrated circuit; Μετατροπείς δεδομένων; Επεξεργασία σημάτων

This thesis deals with the design and implementation of an FPGA based time to digital converter by employing a tapped delay line. Several issues regarding the implementation that are dealt with include clock skew, jitter and non linearity. A down-sampling ap- proach is proposed in order to improv...