| Περίληψη: | The subject of this thesis is the design and verification of the Receiver end, of such a high-speed serial transceiver, suitable for mobile electronic devices (smartphones, tablets etc.), as well as the development of novel design techniques and circuit architectures capable of offering improved performance in several critical subsystems of a HSSI Receiver.
At first, the timing noise (Jitter) sources encountered in serial transmission links are studied and analyzed. A comprehensive method for the calculation of the jitter noise frequency components and the behavioral modeling of jitter noise sources, is proposed. In addition, a Verilog-AMS based HSSI jitter compliant generator, capable of generating random data sequences distorted by Jitter is implemented. The proposed Jitter generator can be easily parameterized in order to be compliant with the specifications of any serial data transmission standard while it can be utilized for the time efficient performance verification of any HSSI Receivers.
Afterwards, the research deals with jitter elimination techniques, related to jitter which affect the transmitted signal due to transmission medium (channel) limited bandwidth. Also, a multi-rate programmable continuous time linear channel equalizer (CTLE), is proposed. The proposed equalizer, by exploiting a coarse small-signal transfer function tuning methodology, which is based on proper re-adjustments of its sub-circuits biasing characteristics, makes feasible its operation in the wide range of frequencies dictated by M-PHY standard. In parallel, it is able to offer optimized power consumption, depending on the input data rate.
Continuing, the study focuses on high precision multiphase clock generation techniques. The generation of multiphase clocks is one of the most important operations, which the timing and synchronization circuits incorporated in HSSI transceivers must be able to accomplish. Two novel Phase Interpolator topologies are proposed, which offer the advantages of high accuracy, multi-rate operation, low power consumption as well as the ability to be easily reformed in order to support higher phase resolution. The ability of the proposed circuits to operate seamlessly in real world HSSI applications, while offering competitive performance characteristics, as compared to already existing topologies in the literature, is demonstrated through the design of a clock and data recovery (CDR) loop which is, perhaps, the most critical component of an HSSI Receiver.
Finally, a GHz range clock frequency multiplier, is proposed. The proposed frequency multiplier, based on a multiphase combination technique, is capable of realizing clock frequency multiplications, with an integer multiplication step. By exploiting the same operation principle, the proposed circuit is also able to perform fractional frequency multiplications, through simple reconfiguration of the phase interpolator circuit.
All circuits proposed in this thesis have been designed according to the specifications implied by MPHY ver. 3.0 standard, which is one of the most popular HSSI protocols for mobile electronic devices. In this way, their ability to be properly adopted in real-world serial data transmission systems is demonstrated.
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