Realizations of fractional-order viscoelastic arterial windkessel models

• Main Author: Μπαξεβανάκη, Κλεονίκη
• Other Authors: Baxevanaki, Kleoniki
• Language: English
• Published: 2021
• Subjects: Fractional-order circuits; Operational transconductance amplifiers; Windkessel models; Bio-impedance; Fractional-order capacitors; CMOS analog integrated circuits; Κυκλώματα κλασματικής τάξης; Τελεστικοί ενισχυτές διαγωγιμότητας; Windkessel μοντέλα; Βιο-εμπέδηση; Πυκνωτές κλασματικής τάξης; Αναλογικά ολοκληρωμένα κυκλώματα CMOS

The present Master Thesis focuses on the implementation of the Windkessel fractional-order model for arterial viscoelasticity, which consists of three elements. Its purpose is to implement the input impedance of the model, as it is a feature used to evaluate hemodynamic parameters and to identify vascular pathologies. The model consists of combining the connection of a resistor in series with two parallel branches of a resistor and a fractional-order capacitor. A fully electronically controlled circuit is introduced which offers the capability for implementing all the states of the arterial system for fractional-orders between 0 and 1. As fractional-order capacitors are not yet commercially available elements, many methods have been proposed to approach their behavior. In the present Thesis an innovative method is proposed for the approximation of the total input impedance of the model, which includes the fractional-order capacitor. This method is based on the concept of curve fitting approximation which approaches the frequency response of the impedance function of the circuit. The model is realized using Operational Transconductance Amplifiers (OTAs) properly connected to each other. In order to achieve the implementation of the model with the minimum number of OTAs, an investigation is performed with two methods, the direct and the partial fraction expansion. The transistors of the OTAs operate in the weak inversion region, achieving low power consumption and low supply voltage. The performance of the proposed scheme is verified through schematic and post-layout levels using Cadence IC design suite and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35μm CMOS technology.