Novel CMOS analog integrated circuits for implementing approximants of the fractional-order Laplacian operator

This Ph.D. Thesis deals with the design of novel CMOS analog integrated circuits, which have been derived through approximation methods of the fractional-order Laplacian operator's implementation. Main attributes of the proposed topologies are the circuit simplicity, due to the small number of...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Μπερτσιάς, Παναγιώτης
Άλλοι συγγραφείς: Bertsias, Panagiotis
Γλώσσα:English
Έκδοση: 2021
Θέματα:
Διαθέσιμο Online:http://hdl.handle.net/10889/15110
Περιγραφή
Περίληψη:This Ph.D. Thesis deals with the design of novel CMOS analog integrated circuits, which have been derived through approximation methods of the fractional-order Laplacian operator's implementation. Main attributes of the proposed topologies are the circuit simplicity, due to the small number of the employed MOS transistors, the reduced power consumption, the limited silicon area and the electronic tuning of their characteristics through appropriate dc bias currents. In recent years, fractional calculus has been applied to circuit design, rendering it one of its most interesting interdisciplinary fields. For the implementation of fractional-order circuits, except for the direct, but commercially unavailable, way of using fractional-order capacitors in the standard topologies, an alternative and, simultaneously, efficient method is the approximation of their behavior through passive or active components. The former implies the utilization of appropriately configured RC networks, easily derived, but not electronically programmable, while the latter favors the electronic adjustment at the expense of the increased active component count. Thus, the main objective of the Thesis is to overcome the existing obstacles through two primary axes. The first one includes the implementation of novel simple structures, using implemented fractional-order capacitors or approximated RC networks, and the realization of capacitorless multi-feedback topologies for performing low-order approximations. The second axis comprises the development of new systematic methods for decomposing the initial higher-order approximated transfer functions into a product or sum of simple lower-order active filter terms. The practical value of the proposed concepts is validated through application examples of various scientific fields. The performance of the presented structures is evaluated through simulation results that have been derived, using the Cadence software and the Design Kit provided by the Austria Mikro Systeme (AMS) CMOS 0.35μm technology process.