| Περίληψη: | Content-Addressable Memories (CAM) are widely used in network infrastructures for the implementation of critical search functions. In the current years, there is an extremely increasing interest in the implementation of Ternary CAMs (TCAMs) in FPGA technology. However, the majority of the proposed implementations does not utilize efficiently the advantages of the FPGA technology and, as a result, they are characterized by inefficient utilization of the available hardware resources and relatively low throughput. The consequence is the inability of the existing implementations to support small TCAM sizes, even in large FPGA devices.
The objective of this diploma thesis is the research and the development of suitable architectures for the implementation of TCAM memories in FPGA technology. These architectures will: a) take into account and exploit the distinct attributes of the very FPGA technology, b) be characterized by high throughput and efficient utilization of the available hardware resources and c) be scalable for the purpose of the efficient implementation of large TCAMs to be possible.
In this thesis, the design of two CAM architectures is developed. These architectures are, particularly, a Binary CAM (BCAM) implemented using the method of hierarchical search, and a Ternary CAM (TCAM) using the method of partitioning the CAM table into smaller sub-tables. The purpose was the utilization of the block-RAMs (BRAMs) of certain FPGA devices to emulate the CAM tables and the examination of the efficiency of the designs in each case.
For each of these two architectures, a base design was implemented. This design was parametric and the parameters were different for each architecture. For the hierarchical-search BCAM, the parameters of the implementation were the size of the CAM, that is the number of entries of the CAM table and the pattern width. For the Scalable TCAM architecture, the parameters were the size of the CAM, the pattern width, three parameters that arrange the internal sub-tables of the architecture, the pipeline stages of the design and a parameter that adjusts the size of the RAMs in which the architecture will be mapped.
The hardware description of the architectures was made in Verilog language. The simulation and the confirmation of their correct operation was done by ModelSim tool of Mentor Graphics. The verification of the results was made possible with the development of testbenches, also described in Verilog HDL.
The implementation of the very designs was made with the use of the Xilinx Vivado Design Suite. The implementation took place for the purpose of conducting experimental measurements over certain metrics. These metrics were the block-RAM (BRAM) utilization of the designs, the maximum frequency (Fmax) that each design can achieve and the resource utilization of the designs, in terms of LUTs and Flip-Flops of the FPGA device. These measurements were extracted by downloading the designs on two different FPGA devices of the Virtex family: VC709 board of the Virtex-7 series and VCU1525 of the Virtex-Ultrascale series. The purpose was to study the behavior of each architecture according to the metrics mentioned previously, as much as to compare the performance of architectures with each other.
After examining the results, the conclusion is that both designs, especially the TCAM design, are scalable with respect to all metrics. The BCAM architecture is really suitable for the implementation of small CAM tables and for lightweight applications, considering its low resource utilization. The TCAM architecture is an ideal candidate for large CAM tables and high throughput applications, since even large designs can reach relatively high frequencies.
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