Realization of non-integer-order impedances for interdisciplinary applications

• Κύριος συγγραφέας: Καλύβα, Παναγιώτα
• Άλλοι συγγραφείς: Kalyva, Panagiota
• Γλώσσα: English
• Έκδοση: 2022
• Θέματα: Fractional calculus; Fractional-order Laplacian operator; Fractional-order elements; Fractional-order circuits; Bio-impedance; RC networks (i.e. Cauer or Foster); Operational amplifiers (opamp); CMOS integrated circuits; Κλασματικός λογισμός; Λαπλασιανός τελεστής κλασματικής τάξης; Στοιχεία κλασματικής τάξης; Κυκλώματα κλασματικής τάξης; Βιομπέδηση; RC δικτυώματα (i.e. Cauer or Foster); Τελεστικοί ενισχυτές; CMOS αναλογικά ολοκληρωμένα κυκλώματα

The subject of this M.Sc. Thesis is the realization of non-integer-order impedances for interdisciplinary applications. More specifically, this Thesis is deals with the consideration of the total impedance of a circuit instead of the intermediate impedance functions, where the realization of this impedance is achieved through the design of a Generalized Impedance Converter (GIC) scheme. Initially, it is presented the suitable curve fitting technique using MATLAB, which is used for approximating the frequency-domain behavior of the total impedance of a fractional-order model and the derived rational integer-order function is then implemented using conventional (i.e. Cauer or Foster) RC networks. The main attractive offered benefit of the proposed concept is that avoiding the approximation of the individual Laplacian operators, the passive component count and by extension the circuit complexity is reduced significantly. Then, it is presented the design of the Generalized Impedance Converter scheme, which consists of five impedances, as well as an Operational amplifier (opamp), which is used twice. This opamp is realized using MOS transistors provided by the AMS (Austria Mikro System) 0.35µm CMOS. The four impedances of the scheme are substituted by resistors and the fifthy impedance, which is the total impedance of the circuit which we study, is substituted by a RC network (i.e. Cauer or Foster). The values of the elements for these networks are calculated applying a n^th order fitfrd approximation on the impedance function of the circut using MATLAB. The last part is the verification of the performance of the proposed scheme through schematic and post-layout simulations, using Cadence and the Design Kit provided by the AMS 0.35µm CMOS technology process.