| Summary: | In this thesis our aim is to study the lightweight encryption Algorithm (LEA) a lightweight block
cipher and propose multiple hardware architectures optimized around execution speed
and/or area. These architectures were first conceptualized by meticulously and methodically
studying LEA. Following this, the hardware designs were described with the hardware
description language VHDL. In order to verify the functionality of the VHDL codes a software
model of LEA was developed in C programming language. These designs were then synthe sized and implemented on three FPGA devices using the Vivado Design suite. Furthermore,
one of the designs was implemented and downloaded on the Zynq-7000 ZC720 Evaluation
board and using the ILA debugging core the functionality of the design was confirmed. Finally,
these designs were compared regarding: 1)maximum frequency, 2) Area utilization 3)Latency
4) Throughput and 5) Throughput per Area. Our goal is to provide insightful comparisons re garding the performance of LEA’s hardware implementations on multiple FPGA platforms.
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