Development of architectures and FPGA implementations of lightweight encryption algorithms
In this thesis our aim is to study the lightweight encryption Algorithm (LEA) a lightweight block cipher and propose multiple hardware architectures optimized around execution speed and/or area. These architectures were first conceptualized by meticulously and methodically studying LEA. Follow...
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nemertes-10889-164662022-09-05T20:18:24Z Development of architectures and FPGA implementations of lightweight encryption algorithms Ανάπτυξη αρχιτεκτονικών και FPGA υλοποιήσεις κρυπτογραφικών αλγορίθμων χαμηλής πολυπλοκότητας Κορόγιαννης, Παναγιώτης Korogiannis, Panagiotis FPGA Lightweight encryption lightweight encryption algorithm (LEA) Κρυπτογραφία χαμηλής πολυπλοκότητας Αλγόριθμοι κρυπτογραφίας In this thesis our aim is to study the lightweight encryption Algorithm (LEA) a lightweight block cipher and propose multiple hardware architectures optimized around execution speed and/or area. These architectures were first conceptualized by meticulously and methodically studying LEA. Following this, the hardware designs were described with the hardware description language VHDL. In order to verify the functionality of the VHDL codes a software model of LEA was developed in C programming language. These designs were then synthe sized and implemented on three FPGA devices using the Vivado Design suite. Furthermore, one of the designs was implemented and downloaded on the Zynq-7000 ZC720 Evaluation board and using the ILA debugging core the functionality of the design was confirmed. Finally, these designs were compared regarding: 1)maximum frequency, 2) Area utilization 3)Latency 4) Throughput and 5) Throughput per Area. Our goal is to provide insightful comparisons re garding the performance of LEA’s hardware implementations on multiple FPGA platforms. H παρούσα διπλωματική εργασία πραγματεύεται την μελέτη του χαμηλής πολυπλοκότητας αλγόριθμου κρυπτογράφησης LEA και την ανάπτυξη αρχιτεκτονικών υλικού βελτιστοποιημένες γύρω από την ταχύτητα εκτέλεσης ή/και το area. Οι αρχιτεκτονικές που αναπτύχθηκαν περιγράφηκαν με τη γλώσσα περιγραφής υλικού VHDL. Για να επαληθευτεί η λειτουργικότητα του κάθε κώδικα VHDL, αναπτύχθηκε ένα μοντέλο λογισμικού του LEA σε γλώσσα προγραμματισμού C. Στη συνέχεια, οι αρχιτεκτονικές συντέθηκαν και υλοποιήθηκαν σε τρεις συσκευές FPGA με τη χρήση του Vivado design suite. Επιπλέον, ένα από τα designs υλοποιήθηκε και μεταφορτώθηκε στην πλακέτα Zynq-7000 ZC720 και με τη χρήση του πυρήνα αποσφαλμάτωσης ILA επιβεβαιώθηκε η λειτουργικότητα του. Τέλος, τα εν λόγω designs συγκρίθηκαν ως προς: 1) μέγιστη συχνότητα, 2)Area 3) καθυστέρηση 4) Throughput και 5) Through per Area. Στόχος μας είναι να συγκρίνουμε την απόδοση των υλοποιήσεων του LEA σε διάφορες πλατφόρμες FPGA. 2022-07-11T11:23:26Z 2022-07-11T11:23:26Z 2022-07-11 http://hdl.handle.net/10889/16466 en application/pdf |
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English |
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FPGA Lightweight encryption lightweight encryption algorithm (LEA) Κρυπτογραφία χαμηλής πολυπλοκότητας Αλγόριθμοι κρυπτογραφίας |
spellingShingle |
FPGA Lightweight encryption lightweight encryption algorithm (LEA) Κρυπτογραφία χαμηλής πολυπλοκότητας Αλγόριθμοι κρυπτογραφίας Κορόγιαννης, Παναγιώτης Development of architectures and FPGA implementations of lightweight encryption algorithms |
description |
In this thesis our aim is to study the lightweight encryption Algorithm (LEA) a lightweight block
cipher and propose multiple hardware architectures optimized around execution speed
and/or area. These architectures were first conceptualized by meticulously and methodically
studying LEA. Following this, the hardware designs were described with the hardware
description language VHDL. In order to verify the functionality of the VHDL codes a software
model of LEA was developed in C programming language. These designs were then synthe sized and implemented on three FPGA devices using the Vivado Design suite. Furthermore,
one of the designs was implemented and downloaded on the Zynq-7000 ZC720 Evaluation
board and using the ILA debugging core the functionality of the design was confirmed. Finally,
these designs were compared regarding: 1)maximum frequency, 2) Area utilization 3)Latency
4) Throughput and 5) Throughput per Area. Our goal is to provide insightful comparisons re garding the performance of LEA’s hardware implementations on multiple FPGA platforms. |
author2 |
Korogiannis, Panagiotis |
author_facet |
Korogiannis, Panagiotis Κορόγιαννης, Παναγιώτης |
author |
Κορόγιαννης, Παναγιώτης |
author_sort |
Κορόγιαννης, Παναγιώτης |
title |
Development of architectures and FPGA implementations of lightweight encryption algorithms |
title_short |
Development of architectures and FPGA implementations of lightweight encryption algorithms |
title_full |
Development of architectures and FPGA implementations of lightweight encryption algorithms |
title_fullStr |
Development of architectures and FPGA implementations of lightweight encryption algorithms |
title_full_unstemmed |
Development of architectures and FPGA implementations of lightweight encryption algorithms |
title_sort |
development of architectures and fpga implementations of lightweight encryption algorithms |
publishDate |
2022 |
url |
http://hdl.handle.net/10889/16466 |
work_keys_str_mv |
AT korogiannēspanagiōtēs developmentofarchitecturesandfpgaimplementationsoflightweightencryptionalgorithms AT korogiannēspanagiōtēs anaptyxēarchitektonikōnkaifpgaylopoiēseiskryptographikōnalgorithmōnchamēlēspolyplokotētas |
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