Design of complementary non-integer power-law filters

• Κύριος συγγραφέας: Παγίδας, Αλέξανδρος
• Άλλοι συγγραφείς: Pagidas, Alexandros
• Γλώσσα: English
• Έκδοση: 2023
• Θέματα: Non integer-order complementary filters; Complementary filters; Fractional-order filters; Power-law filters; Double-order filters; Analog filter designing; Inverse Follow-the-Leader-Feedback (IFLF); Curve-fitting approximation technique; Operational Transconductance Amplifiers (OTAs); Tunable filters; CMOS integrated circuits; Συμπληρωματικά φίλτρα μη-ακέραιας τάξης; Συμπληρωματικά φίλτρα; Φίλτρα κλασματικής τάξης; Φίλτρα κλασματικής δύναμης; Φίλτρα διπλής τάξης; Σχεδιασμός αναλογικών φίλτρων; Τεχνική προσέγγισης προσαρμογής καμπύλης; Τελεστικοί ενισχυτές διαγωγιμότητας; Ρυθμιζόμενα φίλτρα; CMOS ολοκληρωμένα κυκλώματα

This M.Sc. Thesis deals with a novel concept that suggests a new way of implementing non integer-order complementary filters. An innovative approximation method is introduced based on fitfrd command of MATLAB, resulting on less complex integer-order rational transfer functions. This approach offers sufficiently accurate results and uses less active elements for the realization of the proposed filters, in contrast to the conventional methods. In particular, the design of a generalized core structure capable of implementing fractional-order, power-law and double-order low pass filters derived from a first order mother function are presented, as their complementary counterparts can be obtained from a modified version of the corresponding low pass filter. The proposed structure is implemented by utilizing the IFLF (Inverse-Follow-the-Leader-Feedback) multiple-feedback filter topology and using Operational Transconductance Amplifiers (OTAs) as active elements, taking advantage of the electronic tuning capability of their characteristics through appropriate dc bias currents. The selected OTAs design has a low power consumption and operates on low supply voltage, as the MOS transistors of the structure are set to be biased in the weak inversion region. The performance of the proposed scheme is verified through schematic and post-layout levels using Cadence software and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35 μm CMOS technology.