Design exploration of application specific instruction set cryptographic processors for resources constrained systems

The battery driven nature of wireless sensor networks, combined with the need of extended lifetime mandates that energy efficiency is a metric with high priority. In the current thesis we explore and compare the energy dissipation of di fferent processor architectures and how it is associated wit...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Τσεκούρα, Ιωάννα
Άλλοι συγγραφείς: Γκούτης, Κωνσταντίνος
Μορφή: Thesis
Γλώσσα:English
Έκδοση: 2010
Θέματα:
Διαθέσιμο Online:http://nemertes.lis.upatras.gr/jspui/handle/10889/3905
Περιγραφή
Περίληψη:The battery driven nature of wireless sensor networks, combined with the need of extended lifetime mandates that energy efficiency is a metric with high priority. In the current thesis we explore and compare the energy dissipation of di fferent processor architectures and how it is associated with performance and area requirements. The processor architectures are di erentiated based on the datapath length (16-bit, 32-bit, 64-bit and 128-bit) and the corresponding size of the data memories. Our study focuses on AES algorithm, and the indicated processor architectures support AES forward encryption, CCM (32/64/128), CBC (32/64/128) and CTR common modes of operation. In each processor architecture the instruction set is extended to increase the efficiency of the system.