Ultra-low power programmable processor architecture for 60 GHz digital front-end

• Main Author: Μπεμπέλης, Ευάγγελος
• Other Authors: Γκούτης, Κωνσταντίνος
• Format: Thesis
• Language: English
• Published: 2012
• Subjects: Quantization; System scenarios; Fast Fourier transform; 60 GHz; Κβαντοποίηση; Σενάρια συστήματος; Μετασχηματισμός Fourier; 621.392

Modern embedded systems complexity, performance and energy efficiency has been increasing steeply the last few years. An explosive growth in demand for wireless communication is observed as well and modern wireless links are expected to deliver bit rates of several gigabits while consuming even less energy. In order to satisfy these needs new technologies emerge and novel design approaches are put into practice. Communication at 60 GHz is such a technology that is able to deliver high bit rates in short range wireless links. A major motivation to use the 60 GHz spectrum is the worldwide availability which makes exploitation economically viable. Moreover, small wavelength of only 5 mm promises high integration due to small antenna component size which is one of the main bottlenecks for reducing the dimensions. However, increased frequency comes with many disadvantages as well. To increase the market potential of such a new technology the chip design needs to be cheap and energy-efficient. Such cost and energy constrains heavily impact the performance and the quality of both the analog and the digital components of the chip. In the current thesis the design possibilities of a component in the digital baseband of the receiver of such a chip are explored. The component under investigation is a Fast Fourier Transform (FFT) that is used for frequency domain equalization. This part of the receiver is used to reduce the effects of multipath in a non line-ofsight communication environment and as this is a common case in wireless communication the FFT block has been identified as one of the 2 most computational intensive components of the receiver in 60 GHz. This is the main reason why we explore possibilities to further decrease the power consumption of the block while maintaining the performance and the quality of service. To achieve this reduction the possibilities of a new design concept are explored. System Scenarios is a new design concept for embedded systems operating in dynamic environments. Wireless communication systems exhibit high dynamism during their operation on highly varying data streams, providing the System Scenarios huge xvi capabilities. The essential idea behind system scenarios is the classification of the application under investigation from a cost perspective during design time. Then, the classification is exploited during run time resulting to an overall improved implementation of the application. To achieve this the application is broken down to run-time situations (RTS) which are distinguishable operation modes of the application. Then RTSs with similar costs are clustered to form system scenarios. Finally for each scenario a different mapping and scheduling of the application is generated. In the case of the current thesis the application is the FFT and the cost perspective is the power consumption of the component. To exploit the RTS clustering in run time different quantization schemes have been produced. These schemes have been generated based on various properties of the data waveforms in the input of the FFT. The thesis explores the potential of the System Scenarios as well as the application of a quantization methodology for the FFT. Different options of the RTS clustering and the quantization of the FFT block are evaluated in order to come up with a more efficient implementation.