| Περίληψη: | The 21st century is considered as the era of mass communication and electronic information
exchange. There is a dramatic increase in electronic communications and e-transactions worldwide.
However, this advancement results in the appearance of many security issues, especially when the
exchanged information is sensitive and/or confidential. A significant aspect of security is
authentication, which in most of the cases is provided through a cryptographic hash function.
As happens for the majority of security primitives, software design and implementation of hash
functions is becoming more prevalent today. However, hardware is the embodiment of choice for
military and safety-critical commercial applications due to the physical protection and increased
performance that they offer. Hence, similarly to general hardware designs, regarding cryptographic
hash function ones, three crucial issues, among others, arise: performance, reliability, and flexibility.
In this PhD dissertation, hardware solutions regarding cryptographic hash functions, addressing
the aforementionted three crucial issues are proposed. Specifically, a design methodology for
developing high-throughput and area-efficient sole hardware architectures of the most widely-used
cryptographic hash families, i.e. the SHA-1 and SHA-2, is proposed. This methodology incorporates
several algorithmic-, system-, and circuit-level techniques in an efficient, recursive way, exploiting the
changes in the design’s graph dependencies that are resulted by a technique’s application.
Additionally, high-throughput and area-efficient hardware designs for the above families as well as
new ones (e.g. JH and Skein), are also proposed. These architectures outperform significantly all the
similar ones existing in the literature.
Furthermore, a design methodology for developing Totally Self-Checking (TSC) architectures of the
most widely-used cryptographic hash families, namely the SHA-1 and SHA-2 ones is proposed for the
first time. As any RTL architecture for the above hash families is composed by similar functional
blocks, the proposed methodology is general and can be applied to any RTL architecture of the SHA-1
and SHA-2 families. Based on the above methodology, TSC architectures of the two representatice
hash functions, i.e. SHA-1 and SHA-256, are provided, which are significantlty more efficient in terms
of Throughput/Area, Area, and Power than the corresponding ones that are derived using only
hardware redundancy.
Moreover, a design methodology for developing hardware architectures that realize more than
one cryptographic hash function (mutli-mode architectures) with reasonable throughput and area
penalty is proposed. Due to the fact that any architecture for the above hash families is composed by
similar functional blocks, the proposed methodology can be applied to any RTL architecture of the
SHA-1 and SHA-2 families. The flow exploits specific features appeared in SHA-1 and SHA-2 families
and for that reason it is tailored to produce optimized multi-mode architectures for them. Based on
the above methodology, two multi-mode architectures, namely a SHA256/512 and a SHA1/256/512,
are introduced. They achieve high throughput rates, outperforming all the existing similar ones in
terms of throughput/area cost factor. At the same time, they are area-efficient. Specifically, they
occupy less area compared to the corresponding architectures that are derived by simply designing
the sole hash cores together and feeding them to a commercial FPGA synthesis/P&R/mapping tool.
Finally, the extracted knowledge from the above research activities was exploited in three
additional works that deal with: (a) a data locality methodology for matrix–matrix multiplication, (b) a
methodology for Speeding-Up Fast Fourier Transform focusing on memory architecture utilization,
and (c) a near-optimal microprocessor & accelerators co-design with latency & throughput constraints.
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