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04222nam a2200745 4500 |
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OCoLC |
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20170527042025.4 |
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150325s2015 nju ob 001 0 eng |
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|a 2015012035
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|a DLC
|b eng
|e rda
|c DLC
|d OCLCO
|d OCLCF
|d YDXCP
|d EBLCP
|d NLE
|d RECBK
|d DEBSZ
|d DG1
|d IAS
|d IDB
|d MERUC
|d CUS
|d N$T
|d GrThAP
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|a GBB519108
|2 bnb
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|a 922087723
|a 923138054
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|a 9781118861899
|q (electronic bk.)
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| 020 |
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|a 1118861892
|q (electronic bk.)
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|a 9781118861844
|q (electronic bk.)
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|a 1118861841
|q (electronic bk.)
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|z 9781118861882
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|z 1118861884
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|z 9781118861905 (hardback)
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|a (OCoLC)905700275
|z (OCoLC)922087723
|z (OCoLC)923138054
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| 037 |
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|a 9781118861844
|b Wiley
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| 042 |
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|a pcc
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| 050 |
1 |
0 |
|a TK7867.8
|b .D88 2015
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| 072 |
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7 |
|a SCI
|x 021000
|2 bisacsh
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| 072 |
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|a SCI
|x 022000
|2 bisacsh
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| 082 |
0 |
0 |
|a 537/.2
|2 23
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| 084 |
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|a TEC031000
|2 bisacsh
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| 049 |
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|a MAIN
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| 100 |
1 |
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|a Duvvury, Charvaka,
|d 1944-
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| 245 |
1 |
0 |
|a System level ESD co-design /
|c Charvaka Duvvury, Independent ESD Industry Consultant, Texas, USA, Harald Gossner, Intel, Germany.
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| 263 |
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|a 1507
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| 264 |
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1 |
|a Hoboken :
|b John Wiley and Sons, Inc.,
|c 2015.
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| 300 |
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|a 1 online resource.
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| 336 |
|
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b n
|2 rdamedia
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| 338 |
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|a online resource
|b nc
|2 rdacarrier
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| 490 |
0 |
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|a Wiley - IEEE
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| 520 |
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|a "Demystifies the concept of system-level ESD and details its difference from the conventional component level ESD design and testing. Describes the protection elements and designs and focuses on the "co-design", an optimization methodology to address both issues in the same design space"--
|c Provided by publisher.
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| 504 |
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|a Includes bibliographical references and index.
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| 500 |
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|a Machine generated contents note: Chapter 1 Introduction Charvaka Duvvury Chapter 2 Component Versus System Level ESD Charvaka Duvvury and Harald Gossner Chapter 3 System Level Testing for ESD Susceptibility Michael Hopkins Chapter 4 PCB/IC Co-Design Concepts for SEED Harald Gossner and Charvaka Duvvury Chapter 5 Hard Fails & PCB Protection Devices Robert Ashton Chapter 6 Soft Fail and PCB design measures David Pommerenke and Pratik Maheshwari Chapter 7 ESD in Mobile Devices Matti Uusimaki Chapter 8 ESD for Automotive Applications Wolfgang Reinprecht Chapter 9 Futire Applications of SEED Methodology Harald Gossner and Charvaka Duvvury Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost Jeffery C. Dunnihoo Index .
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| 588 |
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|a Description based on print version record and CIP data provided by publisher; resource not viewed.
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| 506 |
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|a Owing to Legal Deposit regulations this resource may only be accessed from within National Library of Scotland. For more information contact enquiries@nls.uk.
|5 StEdNL
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| 650 |
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0 |
|a Shielding (Electricity)
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| 650 |
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0 |
|a Electronic apparatus and appliances
|x Design and construction.
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| 650 |
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0 |
|a Integrated circuits
|x Design and construction.
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| 650 |
|
0 |
|a Integrated circuits
|x Protection.
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| 650 |
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0 |
|a Electrostatics.
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| 650 |
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0 |
|a Static eliminators.
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| 650 |
|
7 |
|a TECHNOLOGY & ENGINEERING / Power Resources / General.
|2 bisacsh
|
| 650 |
|
7 |
|a Electronic apparatus and appliances
|x Design and construction.
|2 fast
|0 (OCoLC)fst00906787
|
| 650 |
|
7 |
|a Electrostatics.
|2 fast
|0 (OCoLC)fst00907767
|
| 650 |
|
7 |
|a Integrated circuits
|x Design and construction.
|2 fast
|0 (OCoLC)fst00975545
|
| 650 |
|
7 |
|a Integrated circuits
|x Protection.
|2 fast
|0 (OCoLC)fst00975587
|
| 650 |
|
7 |
|a Shielding (Electricity)
|2 fast
|0 (OCoLC)fst01115906
|
| 650 |
|
7 |
|a Static eliminators.
|2 fast
|0 (OCoLC)fst01132020
|
| 650 |
|
7 |
|a SCIENCE / Physics / Electricity
|2 bisacsh
|
| 650 |
|
7 |
|a SCIENCE / Physics / Electromagnetism
|2 bisacsh
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| 655 |
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4 |
|a Electronic books.
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| 700 |
1 |
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|a Gossner, Harald.
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| 776 |
0 |
8 |
|i Print version:
|a Duvvury, Charvaka, 1944-
|t System level ESD co-design
|d Hoboken : John Wiley and Sons, Inc., 2015
|z 9781118861905
|w (DLC) 2015008307
|
| 856 |
4 |
0 |
|u https://doi.org/10.1002/9781118861899
|z Full Text via HEAL-Link
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| 994 |
|
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|a 92
|b DG1
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