Computer principles and design in Verilog HDL /

Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills- Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Descrip...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Li, Yamin
Μορφή: Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Solaris South Tower, Singapore : John Wiley and Sons, Inc., 2015.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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082 0 0 |a 621.390285/5133  |2 23 
049 |a MAIN 
100 1 |a Li, Yamin. 
245 1 0 |a Computer principles and design in Verilog HDL /  |c Yamin Li, Hosei University. 
264 1 |a Solaris South Tower, Singapore :  |b John Wiley and Sons, Inc.,  |c 2015. 
300 |a 1 online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b n  |2 rdamedia 
338 |a online resource  |b nc  |2 rdacarrier 
504 |a Includes bibliographical references and index. 
588 |a Description based on print version record and CIP data provided by publisher. 
505 0 |a Title Page; Copyright; Table of Contents; List of Figures; List of Tables; Preface; Chapter 1: Computer Fundamentals and Performance Evaluation; 1.1 Overview of Computer Systems; 1.2 Basic Structure of Computers; 1.3 Improving Computer Performance; 1.4 Hardware Description Languages; Exercises; Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL; 2.1 Logic Gates; 2.2 Logic Circuit Design in Verilog HDL; 2.3 CMOS Logic Gates; 2.4 Four Levels/Styles of Verilog HDL; 2.5 Combinational Circuit Design; 2.6 Sequential Circuit Design; Exercises 
505 8 |a Chapter 3: Computer Arithmetic Algorithms and Implementations3.1 Binary Integers; 3.2 Binary Addition and Subtraction; 3.3 Binary Multiplication Algorithms; 3.4 Binary Division Algorithms; 3.5 Binary Square Root Algorithms; Exercises; Chapter 4: Instruction Set Architecture and ALU Design; 4.1 Instruction Set Architecture; 4.2 MIPS Instruction Format and Registers; 4.3 MIPS Instructions and AsmSim Tool; 4.4 ALU Design; Exercises; Chapter 5: Single-Cycle CPU Design in Verilog HDL; 5.1 The Circuits Required for Executing an Instruction; 5.2 Register File Design 
505 8 |a 5.3 Single-Cycle CPU Datapath Design5.4 Single-Cycle CPU Control Unit Design; 5.5 Test Program and Simulation Waveform; Exercises; Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL; 6.1 Exceptions and Interrupts; 6.2 Design of CPU with Exception and Interrupt Mechanism; 6.3 The CPU Exception and Interrupt Tests; Exercises; Chapter 7: Multiple-Cycle CPU Design in Verilog HDL; 7.1 Dividing Instruction Execution into Several Clock Cycles; 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes; 7.3 Multiple-Cycle CPU Control Unit Design; 7.4 Memory and Test Program 
505 8 |a ExercisesChapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL; 8.1 Pipelining; 8.2 Pipeline Hazards and Solutions; 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes; 8.4 Precise Interrupts/Exceptions in Pipelined CPU; 8.5 Design of Pipelined CPU with Precise Interrupt/Exception; Exercises; Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL; 9.1 IEEE 754 Floating-Point Data Formats; 9.2 Converting between Floating-Point Number and Integer; 9.3 Floating-Point Adder (FADD) Design; 9.4 Floating-Point Multiplier (FMUL) Design 
505 8 |a 9.5 Floating-Point Divider (FDIV) Design9.6 Floating-Point Square Root (FSQRT) Design; Exercises; Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL; 10.1 CPU/FPU Pipeline Model; 10.2 Design of Register File with Two Write Ports; 10.3 Data Dependency and Pipeline Stalls; 10.4 Pipelined CPU/FPU Design in Verilog HDL; 10.5 Memory Modules and Pipelined CPU/FPU Test; Exercises; Chapter 11: Memory Hierarchy and Virtual Memory Management; 11.1 Memory; 11.2 Cache Memory; 11.3 Virtual Memory Management and TLB Design; 11.4 Mechanism of TLB-Based MIPS Memory Management; Exercises 
520 |a Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills- Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design- Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation- Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques- A companion website includes color figures, Verilog HDL codes, extra test benches not found in the book, and PDFs of the figures and simulation waveforms for instructors. 
650 0 |a Verilog (Computer hardware description language) 
650 0 |a Computer engineering  |x Data processing. 
650 7 |a TECHNOLOGY & ENGINEERING / Mechanical  |2 bisacsh 
650 7 |a Computer engineering  |x Data processing.  |2 fast  |0 (OCoLC)fst00872080 
650 7 |a Verilog (Computer hardware description language)  |2 fast  |0 (OCoLC)fst01165388 
655 4 |a Electronic books. 
776 0 8 |i Print version:  |a Li, Yamin.  |t Computer principles and design in Verilog HDL  |d Hoboken : John Wiley and Sons, Inc., 2015  |z 9781118841099  |w (DLC) 2015015679 
856 4 0 |u https://doi.org/10.1002/9781118841105  |z Full Text via HEAL-Link 
994 |a 92  |b DG1