|
|
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| LEADER |
01141nam a2200277 u 4500 |
| 001 |
10105482 |
| 003 |
upatras |
| 005 |
20210117204158.0 |
| 008 |
991213s1990 f eng |
| 020 |
|
|
|a 0 7923 9058 X
|
| 040 |
|
|
|a Βιβλιοθήκη ΙΤΥ
|c Βιβλιοθήκη ΙΤΥ
|
| 040 |
|
|
|a XX-XxUND
|c Βιβλιοθήκη ΙΤΥ
|
| 082 |
1 |
4 |
|a 621.395
|2 20th ed.
|
| 245 |
1 |
0 |
|a Hierarchical Modeling for VLSI Circuit Testing
|c Debashis Bhattacharya, John P. Hayes authors
|
| 260 |
|
|
|a Boston
|b Kluwer Academic Publishers
|c 1990
|
| 300 |
|
|
|c x,159p.:fig.
|
| 650 |
|
4 |
|a ΕΠΕΑΕΚ
|9 116438
|
| 650 |
|
4 |
|a VLSI
|9 24366
|
| 650 |
|
4 |
|a INTEGRATED CIRCUITS
|9 24300
|
| 650 |
|
4 |
|a COMPUTER SIMULATION
|9 24424
|
| 700 |
1 |
|
|a Bhattacharya, Debashis
|9 124675
|
| 700 |
1 |
|
|a Hayes, John P.
|9 105528
|
| 852 |
|
|
|a GR-PaULI
|b ΠΑΤΡΑ
|b ΤΜΗΥΠ
|h 621.395 BHA
|t 1
|
| 942 |
|
|
|2 ddc
|
| 952 |
|
|
|0 0
|1 0
|2 ddc
|4 0
|6 621_395000000000000_BHA
|7 0
|8 NFIC
|9 137612
|a LISP
|b LISP
|c ALFg
|d 2016-04-24
|l 0
|o 621.395 BHA
|p 025000282484
|r 2016-04-24 00:00:00
|t 1
|w 2016-04-24
|y BK15
|x Μεταφορά από Τμ. Μηχανικών ΗΥ & Πληροφορικής
|
| 999 |
|
|
|c 90064
|d 90064
|
