Hierarchical Modeling for VLSI Circuit Testing

Hierarchical Modeling for VLSI Circuit Testing

Λεπτομέρειες βιβλιογραφικής εγγραφής
Άλλοι συγγραφείς:	Bhattacharya, Debashis, Hayes, John P.
Μορφή:	Βιβλίο
Γλώσσα:	English
Έκδοση:	Boston Kluwer Academic Publishers 1990
Θέματα:	ΕΠΕΑΕΚ VLSI INTEGRATED CIRCUITS COMPUTER SIMULATION

Παρόμοια τεκμήρια

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